Light emitting devices and arrays with pockets

ABSTRACT

Techniques, devices, and systems are disclosed and include LEDs with a first flat region, at a first height from an LED base and including a plurality of epitaxial layers including a first n-layer, a first active layer, and a first p-layer. A second flat region is provided, at a second height from the LED base and parallel to the first flat region, and includes at least a second n-layer. A sloped sidewall connecting the first flat region and the second flat region is provided and includes at least a third n-layer, the first n-layer being thicker than at least a portion of third n-layer. A p-contact is formed on the first p-layer and an n-contact formed on the second n-layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims continuation priority to U.S. application Ser.No. 17/518,699, filed on Nov. 4, 2021, which claims continuationpriority to U.S. application Ser. No. 17/030,674, filed on Sep. 24,2020, now U.S. Pat. No. 11,271,033, issued on Mar. 8, 2022, which is adivisional application of U.S. application Ser. No. 16/144,751, filedSep. 27, 2018, now U.S. Pat. No. 10,811,460, issued Oct. 20, 2020 under35 U.S.C. § 121, U.S. application Ser. No. 17/030,674 also claimscontinuation priority under 35 U.S.C. § 120 to U.S. application Ser. No.17/030,542, filed on Sep. 24, 2020, now U.S. Pat. No. 11,201,265, issuedon Dec. 14, 2021, which claims continuation-in-part priority to U.S.application Ser. No. 16/586,882, filed on Sep. 27, 2019, now U.S. Pat.No. 10,964,845, issued on Mar. 30, 2021, which claimscontinuation-in-part priority to U.S. application Ser. No. 16/584,941,filed on Sep. 26, 2019, now U.S. Pat. No. 10,923,628, issued on Feb. 16,2021, which claims continuation-in-part priority to U.S. applicationSer. No. 16/144,751, filed on Sep. 27, 2018, now U.S. Pat. No.10,811,460, issued on Oct. 20, 2020, and to Europe Ser. No. 18209260.1filed on Nov. 29, 2018, the disclosures of which are incorporated hereinby reference in their entireties.

BACKGROUND

Light emitting diodes (LEDs) have emerged as an appealing light sourcefor many applications. From road signage and traffic signals, LEDs arebecoming dominant in general lighting, automotive, mobile electronics,camera flash, display backlighting, horticulture, sanitization and otherapplications.

SUMMARY

Techniques and devices are disclosed that include LEDs with a first flatregion, at a first height from a reference point (e.g., a base of anLED, a contact, a backplane, etc.), including a plurality of epitaxiallayers such as a first n-layer, a first p-layer, and a first activelayer. A second flat region at a second height from the first referencepoint and that is different than the first height (e.g., the first flatregion may be 10 micrometers higher than the second flat region) andparallel to the first flat region includes at least a second n-layer.Sloped sidewalls connect the first flat region and the second flatregion and include at least a third n-layer. The p-layer of the firstflat region is thicker than at least a portion of the sloped sidewalls.A p-contact is formed on the first p-layer and an n-contact is formed onthe second n-layer.

Techniques and devices are disclosed that include a patterned substratehaving a patterned region forming mesas with non-patterned surfaces, andsloped sidewalls extending from the non-patterned surfaces toward abottom surface of the patterned substrate. A continuous epi layer is onthe patterned substrate, the continuous epi layer comprising an n-layeradjacent the patterned substrate, a p-layer, and an active layerpositioned between the n-layer and the p-layer, the continuous epi layerhaving a first portion, a second portion and a third portion, the firstportion positioned adjacent to the non-patterned surfaces of the mesas,the second portion positioned adjacent the bottom surface, and a thirdportion positioned adjacent the sloped sidewalls, the third portionhaving a thickness less than a thickness of the at least one of thefirst portion and the second portion, p-contacts electrically coupled tothe first portion of the epi layer, n-contacts electrically coupled tothe second portion of the epi layer and extending vertically from thesecond portion of the epi layer toward a plane extending laterally fromthe non-patterned surface of the mesas, insulating material positionedbetween the third portion of the continuous epi layer and the n-contact.

Techniques, and devices are disclosed that include an array of lightemitting diodes (LEDs), that include a backplane, a plurality of LEDs,such that each LED includes an n-contact and a p-contact electricallycoupled to the backplane, a plurality of pockets having a base layer anda top layer connected via a sloped sidewall layer extending from thebase layer outwardly and away from the backplane, the base layer, thetop layer and the sloped sidewall layer comprising a light emittingactive region, the sloped sidewall layer is thinner than at least one ofthe base layer and the top layer. The n-contact may extend verticallyfrom the backplane towards a plane extending laterally from the toplayer of the plurality of pockets, the n-contact surrounding the baselayer and the top layer and providing optical isolation between adjacentLEDs of the plurality of LEDs. A p-contact may be electrically coupledto the base layer, and an insulating material may be positioned betweenthe n-contacts and the p-contacts attached to the plurality of pockets.

BRIEF DESCRIPTION OF THE DRAWINGS

A more detailed understanding may be had from the following description,given by way of example in conjunction with the accompanying drawingswherein:

FIG. 1A (from Chang C-Y., Li H. and LU T-C., Compound Semiconductor,Vol. 21, Issue VII, p 48-52, 2015) illustrates a variation of epitaxialgrowth rate on different crystallographic planes for a V-pit for InGaNmulti-quantum wells, and correlation to epitaxial structure on patternedsubstrates;

FIG. 1B illustrates a LED growth/regrowth with thinner deposition on asidewall of a patterned template;

FIGS. 2A and 2B illustrate a LED growth/regrowth on a patternedtemplate;

FIG. 3 illustrates the LED of FIG. 2A with added P- and N-contacts;

FIG. 4 illustrates a LED deposition on a patterned substrate;

FIGS. 5A-5L illustrate a monolithic LED array e.g., Thin Film Flip Chip(TFFC) at various stages of the workflow;

FIG. 6A illustrates a method of producing a monolithic LED array (e.g,TFFC);

FIG. 6B illustrates a method of producing a light emitting device (LED)having epitaxy layers;

FIG. 6C illustrates another method for producing a light emitting device(LED) having epitaxy layers;

FIG. 6D illustrates another method for producing an LED array;

FIGS. 7A-7I illustrate a monolithic LED array e.g., Vertical InjectionThin Film (VTF) at various stages of the workflow;

FIG. 8 illustrate a method of producing a monolithic LED array (e.g,VTF);

FIG. 9 illustrates a LED by growth/regrowth on a patterned template (notlimited to depicted circular cross-section);

FIG. 10A illustrates a LED structure on a patterned substrate;

FIG. 10B illustrates a LED structure on a patterned body including botha patterned substrate and patterned n-layer;

FIGS. 11A and 11B illustrate TFFC versions of LEDs with attached lens;

FIGS. 12A and 12B illustrate chip scale package (CSP) versions of LEDswith attached lens;

FIG. 13 illustrates an alternative LED embodiment requiring lessprocessing (p-side sidewall);

FIGS. 14A and 14B illustrate alternative embodiments for substrate(shown) or template pattern angle;

FIGS. 15A-15C illustrate embodiments for different cross-sections ofsubstrate (shown) or template patterns (for example, rectangular,triangular, polygonal);

FIG. 16A illustrates an embodiment of LED with isolated active regionvia “pinch-off”; and FIG. 16B illustrates a call-out of FIG. 16A to showrelative layer sizing of the pinch-off zone;

FIG. 17 illustrates a LED on multilevel patterned substrates;

FIG. 18 illustrates an isolated LED realized through use of multilevelpatterned substrate;

FIGS. 19A and 19B illustrate a monolithic TFFC array of LEDs usingphosphor conversion and optical isolation that does not require pick andplace;

FIG. 20 illustrates a LED unit cell of monolithic TFFC array usingphosphor conversion and optical isolation;

FIGS. 21A and 21B illustrate a monolithic VTF array of LEDs usingphosphor conversion and optical isolation that does not require pick andplace;

FIG. 22 illustrates a LED unit cell of monolithic VTF array usingphosphor conversion and optical isolation;

FIG. 23 illustrates a diagram of an example system that may be used toimplement all or some of the embodiments described herein;

FIG. 24 illustrates a unit cell of a monolithic array of substrate-onLEDs; and

FIGS. 25A and 25B illustrate a monolithic array of substrate-on LEDsthat do not require pick and place.

DETAILED DESCRIPTION

Typical benefits of LEDs compared to competing light sources includeincreased efficiency, longer lifespan and adaptability to a largevariety of form factors. One type of LED that exhibits leadingefficiency and lifespan is an inorganic semiconductor-based LED,hereafter simply referred to as LED. In this type of LED, the diodetypically includes one or more semiconductor-based quantum welllight-emitting layers sandwiched between thicker semiconductor-basedouter layers conducting the current.

An emerging application of LEDs is in directly illuminated displays,where the increased efficiency and longer lifespan of LEDs makes theLEDs an attractive replacement for organic LEDs (OLEDs), which are thecurrent dominant technology. The high luminous efficacy of LEDs (lumensper watt; >100 Lm/W) allows for lower power consumption usage comparedto OLEDs, as well as reduced heat generation. The reduction in heat, inconjunction with the increased chemical stability of inorganic LEDscompared to OLEDs improves the relative lifetime of a correspondingdisplay. Similarly, the higher efficacy of inorganic LEDs allows for asmaller chip area to achieve a given system brightness, which reducescost compared to an OLED array. This is particularly applicable to largearea displays such as monitors. In order to deploy LEDs for high densitydisplay applications or for large area, medium density applications, theLED unit is desired to have characteristic dimensions (e.g., height,width, depth, thickness, etc.) of less than 100 micrometers with typicalvalues of less than 50 micrometers, less than 25 micrometers, includinga range of 1.5 to 25 micrometer, and all subranges therebetween. Thisclass of LEDs is commonly referred to as micro-LEDs (uLEDs). Theembodiments disclosed herein may generally be applied to uLEDs withcharacteristic dimensions of less than 100 micrometers, though it willbe understood that the embodiments are not limited only to uLEDs.

As the dimensions of LEDs are reduced to below 100 micrometers, it isexpected that luminous efficacy may suffer additional losses compared toLEDs with characteristic dimensions of 100 micrometers or larger. Themain reason is that in a typical LED process, an etch cutting throughthe epitaxial active region borders the electrically active part of thedevice. Defects at the etched sidewall accelerate non-radiative carrier(electron and hole) recombination where heat is generated instead oflight. Also, the defects can compensate p-type material, converting thelayer to n-type and creating a path for leakage currents. In eithercase, what is known as the sidewall or edge effect creates aninefficient border area. As device dimensions and drive currentsdecrease, the impact of the sidewall or edge effects increase. Forexample, in AlInGaP devices, non-radiative centers at the die edge mayreduce light emission over a range of order of 5 micrometers, so a 50micrometer device might suffer a 20% deficit in efficiency, while a 15micrometers device would suffer a greater than 50% deficit inefficiency.

Attempts have been made to passivate the sidewalls to reduce oreliminate recombination that typically involve deposition of passivationlayers including certain epitaxial layers and dielectric layers. Theseattempts, however, can lead to larger manufacturing complexity, highercost and less flexibility in layout design of LED devices. In addition,the effectiveness of proposed passivation layers has not beenestablished conclusively, as it depends on the interaction between theLED active region and the deposited passivating material. It is notclear, for example, to what extent the passivating material preventscarrier transport to the sidewall.

One or more embodiments described herein address the aforementionedluminous efficacy loss mechanism and are based upon established carriertransport physics that is independent of the dimension of the LED. Inaddition, one or more embodiments allow for economical fabrication ofLEDs and flexibility in fabrication of monolithic LED devices (e.g.,displays) from a wafer. One or more embodiments described hereinadvantageously exclude a passivation layer on sidewalls (e.g., slopedregions). In one or more embodiments, the sidewalls or sloped regionsexclude a dielectric layer.

When using traditional techniques for fabricating LED displays, it iscommonly understood that each LED die or group of LED dies aretransferred to a backplane such as a thin film transistor (TFT)backplane by pick-and-place methods. The backplane may be configured toindividually address each of a plurality of LEDs in an array of LEDs,and may be configured such that that at least one of: a colortemperature, an intensity, or a source pattern for each LED areadjustable via the backplane (e.g., if the plurality of LEDs areconfigured to emit white light). When the display resolution and sizeincrease, the number of transferred dies increases. The cost tofabricate HD or 4K display panels, requiring millions of die transfers,becomes too high to realize commercially viable products. Directemission LEDs may be difficult to fabricate because of the requirementsfor uniform emission wavelength and minimal color shift with drivecurrent. Red emitting LEDs based upon AlInGaP may suffer fromtemperature sensitivity of efficiency.

As used herein, a “patterned body” is a structure having patternedregions and non-patterned regions. In an embodiment, the patterned bodyis a patterned substrate; exemplary substrates are: sapphire, silicon,silicon carbide, GaN and GaAs substrates. In an embodiment, thepatterned body is a patterned template; exemplary templates aren-layers. In an embodiment, the patterned body is a combination of apatterned substrate and a patterned template. In an embodiment, thepatterned body is a combination of a planar substrate and a patternedtemplate. According to one or more embodiments disclosed herein, aplurality of LEDs may be formed at a wafer level (e.g., by growing on apatterned substrate such as, for example, a patterned sapphire substrate(PSS), or n-layer, as disclosed herein) and additional material orcomponents (e.g., phosphor material, secondary optics, etc.) may bedeposited into or over pockets of each individual LED prior to theplurality of LEDs being bonded to a backplane. Alternatively, theplurality of LEDs may be formed at a wafer level and additional materialor components may be deposited into or over pockets of each individualLED after the plurality of LEDs have been bonded to a backplane.Notably, in accordance with one or more disclosed embodiments, a groupof LEDs prepared on a patterned body may be bonded to an LED backplaneas an alternative to implementing a pick-and-place technique. Accordingto an embodiment, a plurality of LEDs may be formed at a wafer level andmay be bonded to a backplane prior to etching or otherwise separatingthe plurality of LEDs on the backplane into a smaller array of LEDs.According to another embodiment, a plurality of LEDs may be formed at awafer level and may be etched or otherwise separated into a smallerarray of LEDs after being bonded to a backplane.

Embodiments described herein include: a single color monolithic microdisplay (e.g., a red, a green, or a blue), a direct emission display, ora monolithic full color display that eliminates the costly die-transferand simplifies the fabrication process. As an example, a direct emissiondisplay comprises an array of LEDs, whose active layers directly emitlight, and may not include a phosphor converting element as part of oneor more LEDs within the array of LEDs. Also, with respect tophosphor-converted LEDs, monolithic Thin Film Flip Chip (TFFC) orVertical Injection Thin Film (VTF) arrays may be less challenging tomanufacture because the requirements on wavelength uniformity andwavelength shift with drive current are reduced, and the growth ofuniform, high efficiency, low droop epitaxies with less wavelength shiftis easier in the near-UV (NUV) (e.g., approximately 400 nm wavelength),blue (e.g., royal blue at approximately 450 nm), or like emission. Thegrowth of NUV, blue, or like emitting epitaxies is known to be lesschallenging than, for example, green emitting epitaxy. According toembodiments disclosed herein, an LED structure (e.g., uLED structure)including a plurality of LEDs, where adjacent LEDs are separated bystreets (e.g., “S” of FIG. 1B), may be segmented from a wafer of alarger number of fully or partially formed LEDs. Although limited torelatively small physical dimensions, the described embodiments mayenable commercialization of display panels of greater than 4Kresolution, in a compact form factor suitable forVirtual/Mixed/Augmented Reality hardware, projectors, and high endwearables. The provided display may be a thin film device limited inflexibility by the TFT backplane and may support flexible or curveddisplays. Finally, coupling of optical elements may be done in anefficient parallel fashion with, for example, over-molding.

Embodiments described herein include light emitting devices, such asLEDs, that can be implemented in a color display and that include asemiconductor structure that has a plurality of epitaxial layers. Theepitaxial layers may include one or more of an n-layer, n-layer growthor regrowth, p-layer, active layer, electron blocking layer, setbacklayer, and the like. The semiconductor structure of a light emittingdevice may include a first flat portion, a second flat portion recessedfrom and parallel to the first flat portion, and a sloped sidewall thatconnects the first flat portion to the second flat portion. According toone or more embodiments, the light emitting device may include an arrayof LEDs that are formed using a patterned substrate that has a patternedregion forming mesas with a bottom surface and sloped sidewallsextending from the bottom surface toward a non-patterned surface of thepatterned substrate. For example, FIG. 5A shows a patterned substrate505 that includes a patterned region 502 and non-patterned region 501.The patterned region 502 includes a bottom surface 503 a (or second flatregion), and sloped sidewalls 503 b. The non-patterned region 501includes the non-patterned surface 503 c (or first flat region) which isconnected to the bottom surface via the sidewall 503 b. As appliedherein, a first flat region may be referred to as a non-patternedsurface (e.g., single LED) or non-patterned surfaces (e.g., array ofLEDs) and a second flat region may be referred to as a bottom surface,and vice versa. The resistivity of the sidewall junction may be at least10 times greater than the resistivity of the junction between the topand base layer.

A first flat portion may be at a first height relative to a referencepoint (e.g., from a backplane, from a contact, from an LED layer orcomponent) and the second flat portion may be at a second heightrelative to the same reference point. The difference in the first heightand the second height may be between 1 micrometers and 50 micrometersaccording to an implementation and between 1 micrometers and 10micrometers according to another implementation. For example, the top ofa first flat portion may be at a height of 13 micrometers from themiddle of a backplane and the top of a second flat portion may be at aheight of 8 micrometers from the middle of the same backplane such thatthe difference in height between the first flat portion and the secondflat portion is 5 micrometers. According to embodiments, the thicknessof an n-layer in the first region may at least approximately equal thethickness of the n-layer in the second region plus the differencebetween the height of the first flat region and the height of the secondflat region. According to embodiments, the first flat portion may bevertically offset from the second flat portion such that a lineextending vertically from the second flat portion would not intersectwith the first flat portion and vice versa. According to an embodiment,the first flat portion may be shaped as a polygon as shown in FIG. 5L.According to an embodiment, the first flat portion may have a thicknessbetween 1 micrometers and 50 micrometers.

Epitaxial layers in the sloped sidewall may have a thickness that isless than 80% of their corresponding thickness of the first flat portionand/or the second flat portion. Reference herein to thickness means athickness orthogonal to an underlying surface, for example, a flatportion or sloped sidewall. For a given doping level, the electricalresistance of the p-layer is inversely proportional to the layerthickness, thus the reduction of thickness of the p-layer in the slopedregion increases electrical resistance and reduces parasitic holeleakage currents between the first flat portion and the second flatportion or sloped sidewalls. For example, a 50% reduction in thicknessmay increase the resistance by 200% and reduce parasitic hole currentsby a factor of 2. Similar reduction of the thickness of the quantum well(QW) active region in the sloped sidewall will increase the energybandgap of the crystal in that region. The higher energy bandgap willcreate an energy barrier and restrict carriers to the first portion. Itshall be noted that “restrict” may result from choking or blocking ofcarriers as applied in this disclosure. For example, a 50% decrease inQW thickness may increase the energy bandgap by ˜75 meV and provideeffective confinement. A second effect of the thinner QW active regionis to increase the forward voltage of the p-n junction in the slopedsidewalls. Parasitic hole currents that flow from the first region tothe sloped sidewall will be blocked from flowing through the p-njunction in the sloped sidewall. The combined effect of thinner p-layerand QW active region in the sloped sidewall may effectively causegreater than 90% of a forward bias hole injection to be confined to thefirst flat portion of an LED. According to embodiments, the height ofthe sloped sidewall may be between 1 micrometers and 10 micrometers andthe angle created by the first flat region and the sloped sidewalls maybe between 45 degrees and 160 degrees. The sloped sidewalls may at leastpartially or fully surround the first flat region of each LED and thesecond flat region may at least partially surround the sloped sidewalls.

According to embodiments, the height of the sloped sidewalls may bebetween 1 micrometers and 10 micrometers, and the angle created by thefirst flat region and the sloped sidewalls may be between 45 degrees and160 degrees. The sloped sidewalls may at least partially or fullysurround the first flat region of each LED and the second flat regionmay at least partially surround the sloped sidewalls.

In accordance with embodiments described herein, a patterned body, e.g.,a patterned template or substrate, such as the patterned substrate shownin FIG. 5A is provided and combined with appropriate growth conditionsto modify the epitaxial layer structure on the semi-polar crystal planespresent at the device sidewalls. A resulting polygonal array of LEDsbased on the patterned substrate is shown in 5L. Specifically, thegrowth rate on the sloped sidewalls is greatly reduced relative to lowindex planes. With appropriate epitaxial structure design, p-sidecarrier transport along the sidewalls is blocked because of highelectrical resistance and increased bandgap while n-side lateral currentflow is maintained. Current injection is intrinsically limited to thefirst flat region (e.g., non-patterned region) via the reflectivep-contact and p-side leakage currents from p to n-contact are pinchedoff. Post-growth processing steps normally required to isolate thecurrent injection and passivate the damage of isolation etching areeliminated. Cost saving and a reduction in scale of the devices arerealized since each lithography step/thin film layer requires somelateral spacing to accommodate edge effects, misalignment, and runout.Therefore, in accordance with embodiments disclosed herein, lightemitting devices having a lateral extent of less than 10 micrometers mayincorporate epitaxial structures greater than 5 micrometers thick.Standard processing techniques may not be practical for fabricatingdevices having an aspect ratio greater than 2. As an example, with theproposed embodiments, fabrication LEDs with two light-emitting junctionsand a tunnel junction disposed in between, and having a less than 10micrometers lateral extent, maybe realized. Further, the phenomenon ofreduced sidewall growth rate is analogous to that observed in MOCVDgrowth of InGaN LEDs on surfaces containing V-pits.

FIG. 1A (from Chang C-Y., Li H. and LU T-C., Compound Semiconductor,Vol. 21, Issue VII, p 48-52, 2015) illustrates variation of epitaxialgrowth rate on different crystallographic planes for a V-pit for InGaNmulti-quantum wells, and correlation to epitaxial structure on patternedsubstrates. The TEM in FIG. 1A clearly shows the differences in growthrates between crystallographic planes. In the TEM image, the top part ofan epitaxially deposited InGaN where the V-pit feature that is formed onthe underlying material is decorated on its sidewalls. The thickness ofthe dark layers decreases dramatically on the inclined sidewalls of theV-pit feature. The patterned body (e.g., substrate and template) designsherein leverages the same effect to produce the thin sidewall layers inthe context of deposition of epitaxial layers for uLEDs discussed above.An advantage of this technique is the elimination of a need to passivatesidewalls.

FIG. 1B illustrates a LED 100 growth/regrowth with thinner deposition ona sidewall of a patterned template. LED 100 growth/regrowth may be grownon a patterned substrate (not shown) or template (e.g., n-layer) 110. Asdepicted in FIG. 1B, the number of steps in the patterned n-layer 110may be N=1. A depiction of a patterned n-layer with N=2 is shown asn-layer 110.1. The pattern may include a width w, street width s, aheight h, and an angle φ. Width w may be defined as the width of thepattern at its base. Width w may range from (or be approximately) 1-50micrometers. Height h may be defined as the height from the base to thetop of the pattern. Height h may range from (or be approximately) 1-10micrometers. Street width s may be defined as the amount of the n-layer110 (or substrate if the substrate is patterned) that does not includethe pattern on it. Street width s may be equal on the sides of thepattern for patterns that are centered, or approximately centered, withn-layer 110. Street width s may range from (or be approximately) 1-5micrometers. The angle the top of the pattern of n-layer 110 createswith the sidewall of the pattern may be defined as angle φ. Angle φ mayrange from (or be approximately) between 45 degrees and 160 degrees.

On the patterned n-layer 110, there may be an epitaxially grown p-layer120. This p-layer 120 may take the shape of the patterned n-layer 110and may maintain a thinner deposition on the sidewall. In betweenn-layer 110 and p-layer 120 is an active layer 115. A siliconeencapsulant and/or an epoxy encapsulant may be provided on the secondflat portion of the n-layer and/or a light converting phosphor, asfurther described herein.

The described embodiments can be implemented with sapphire, silicon,silicon carbide, GaN and GaAs substrates or through patterning (n-layer)templates (for example by electron beam lithography) deposited directlyon them (in this case, either patterned or planar). Material depositioncan be accomplished with established methods for macroscopic LEDs, suchas, but not limited to MOCVD, MOVPE, HVPE MBE, RPCVD, Reactive andNon-reactive Sputtering. For example, one can use direct MOCVD growth onthe substrate or in conjunction with different deposition technologies,such as reactive sputtering or PVD, to prepare the surface for epinucleation (for example, aluminum nitride). Moreover, the resultingepitaxial structures are compatible with standard semiconductorprocessing steps, such as electrical contact formation, opticalisolation layers (for example, silicon nitride, silicon oxide, titaniumoxide, etc.), growth substrate removal, and interconnects(electroplating, evaporation, etc.). The final result may be singulatedelement LEDs for large area displays with sparse arrays or arrays (e.g.,highly dense monolithic) for compact displays which may include LEDsthat are single color, multi-color, or direct emission. Arrays of LEDsmay be shaped in any applicable manner including rectangular arrays,circular arrays, hexagonal arrays, trapezoidal arrays, or any otherconfiguration including those that do not form a pre-determined shape.

The techniques described herein may be implemented by forming all orpart of a plurality of LEDs as a wafer of LEDs that are formed andsingulated to generate arrays of LEDs. For example, a wafer of 1000 LEDsmay be formed and singulated to form a subset array of LEDs to beimplemented in a 4 inch by 6 inch display. The LEDs in the subset arrayof LEDs may all emit light in the same range of wavelength or,alternatively, the subset array of LEDs may include sets of LEDs thatemit different wavelengths (e.g., the subset array of LEDs may include aplurality of red, green, and blue LEDs). According to embodiments, anarray of LEDs may be singulated from a wafer, and the first flat regions(i.e., top flat regions) of the LEDs in the array may form a regulararray of similar polygons with periodicity between 4 micrometers and 40micrometers, each polygon having a lateral extent between 2 and 100micrometers. According to embodiments, the first flat region may beshaped as a prism having a lateral extent between 2 micrometers and 100micrometers and a thickness between 1 micrometers and 50 micrometers.

The described embodiments do not limit the variety of substrate patternsand patterning technologies that can be used. They are compatible withwet-etch or dry etch processes, electron beam lithography amongstothers. They can also benefit from multilevel patterning technologies,especially those that can be fabricated in a self-aligned way, e.g.,using lithography through deposition of different thickness resists tocontrol etch rates. They are compatible with and can benefit from, whennecessary, selective etching to further isolate edge/sidewall of theactive region from the p-side/n-side. An active region as applied hereinmay be any applicable active region such as a homo junction, doublejunction, hetero structure junction (e.g., a first material is adifferent bandgap than a second material), double hetero structurejunction, a single quantum well, a multiple quantum well, or the like.

Generally, the disclosed embodiments are based upon growth of an LEDstructure on a patterned body such as a patterned template deposited ona planar substrate, or growth on a patterned substrate. By way ofexample, FIGS. 2A and 2B illustrate a LED growth/regrowth on a patternedtemplate. FIG. 2A illustrates a LED 200 growth/regrowth with N=1 andFIG. 2B illustrates a LED 280 growth/regrowth with N=2. Referring now toeither, or both, of FIGS. 2A and 2B, a substrate 205 is utilized.Substrate 205 may take the form of planar sapphire, GaN, Si, SiC, GaAs,for example. Substrate 205 may have deposited thereon an n-layer 210.The n-layer 210 may be deposited as an initial template layer for theshape and structure desired. For example, the layer may include a widthw, street width s, a total height h and a lower level light h₂, and anupper angle φ₁. and lower angle φ₂. While the present examplesillustrate each shoulder width as identical, such a configuration is notrequired. FIG. 2A illustrates a single step, while FIG. 2B illustrates adual step. In essence, n-layer 210 may be patterned by varying anyvariable include height h (e.g., between 1 micrometers and 10micrometers), width w, street width s, number of steps n and angle φ(e.g., between 45 degrees and 160 degrees) to achieve a desired shape.While each of FIGS. 2A and 2B generally show a trapezoidal pattern witha squared shape, the perimeter shape may be from circular to polygonal,symmetric or elongated.

An active layer 215 may be deposited on n-layer 210 taking the shape andform of n-layer 210 including height h, width w, street width s, numberof steps n and angle φ. Active region 215 may be formed as a layer, alsoreferred to as a cavity, and may take the form of a layer of pGaN. Aswould be understood by those possessing an ordinary skill in thepertinent arts, GaN is a binary III/V direct bandgap semiconductorcommonly used in light-emitting diodes. GaN has a crystal structure witha wide band-gap of 3.4 eV that makes the material ideal for applicationsin optoelectronics, high-power and high-frequency devices. GaN can bedoped with silicon (Si) or with oxygen to create an n-type GaN and withmagnesium (Mg) to create a p-type GaN.

A p-layer 220 may be deposited on active layer 215 taking the shape andform of the active layer 215 including height h, width w, street widths, number of steps n and angle φ. A p-layer 220 may be replaced with atunnel junction layer, which consists of heavily Mg doped p++-layer andheavily Si-doped n++-layer. The tunnel junction layer may result in anepitaxial structure that includes a junction n-layer, a second activelayer, a junction p-layer, a tunnel junction disposed above a structureincluding at least a p-layer, a first active layer, and an n-layer suchthat the tunnel junction layer faces the p-layer. Replacing highresistance p-GaN layer with low-resistance n-GaN layer enables facileformation of ohmic contact and improved current spreading, and thereforea reduced contact metal footprint. The resulting epitaxial structure iscompatible with the semiconductor fabrication process described herein.

FIG. 3 illustrates a LED of FIG. 2A with p-contact and n-contacts. LED300 includes the elements of LED 200 including n-contact 330 andp-contact 325. N-contact 330 may be formed by exposing n-layer 210 andforming the n-contact 330 thereon. P-contact 325 may be formed onp-layer 220. It will be understood that any contact described herein mayinclude any applicable conductive material (e.g., silver) and may bepositioned adjacent to and/or in connection with an indium tin oxide(ITO) layer. For example, an ITO layer may be provided between a contactand a backplane. Further, as a specific example, an n-contact asdisclosed herein may be fully or partially composed of an aluminum oraluminum alloy.

FIG. 4 illustrates a LED 400 deposition on a patterned substrate 405.Substrate 405 may be formed of sapphire, GaN, Si, SiC, GaAs, forexample. As with the n-layer in the previous example, the substrate 405may be patterned by varying any variable including height h, width w,street width s, number of steps n and angle φ to achieve desired shapeand a perimeter shape may vary from circular to polygonal.

The n-layer 410 may be deposited on the patterned substrate 405 takingthe shape and form of substrate 405 including height h, width w, streetwidth s, number of steps n and angle φ.

An active layer 415 may be deposited on n-layer 410 taking the shape andform of n-layer 410 including height h, width w, street width s, numberof steps n and angle φ imparted from substrate 405.

A p-layer 420 may be deposited on active layer 415 taking the shape andform of active layer 415 including height h, width w, street width s,number of steps n and angle φ imparted from substrate 405. As discussedwith respect to FIG. 3, n- and p-contacts may be formed on LED 400.

The embodiments depicted in FIGS. 2-4 are primarily representative LEDelements. The mechanism of the patterned body growth may determine therange of shapes and dimensions of light-emitting flat regions (e.g.,mesas), non-light emitting sidewall areas, and non-light emittingstreets. Reflective p-contacts may cover the mesas, and n-contacts maybe formed in the streets as shown in FIG. 3. Reflective design elementssuch as TiOx-silicone suspensions and non-conductive reflectivestructures may be employed on the sidewalls to enhance efficiency andoptically isolate devices. The body (substrate or template) patterningmay include a very fine nanometer scale (sub-micron) patterning (randomor periodic) to enhance optical outcoupling into the phosphor layer. Asilicone encapsulant and/or an epoxy encapsulant may be provided overthe phosphor layer. The roughening may be created after substrateremoval by nano-imprint lithography and etching, photo electrochemicaletching or similar methods.

Combinations of the growth in forming LED 200 and LED 400 may be used.Combinations of the techniques may be used to achieve desired thicknessratio between flat areas and sidewalls. The thinner sidewalls in each ofLED 200 and LED 400, and in techniques that are combined, leveragethinner deposition on sidewall to reduce surface sidewall recombination,improve performance, reduce processing and fabrication cost, and exposen-layer and make n- and p-contacts (similar to FIG. 3). The thinnersidewalls may increase p-side electrical resistance and reduce leakagecurrents. The thinner QW in the active region may increase the bandgapenergy of the sidewall material, creating a hole barrier and restrainingrecombination to the semiconductor under the p-contact 325. Theelimination of process steps to isolate n and p-contact reducesfabrication cost and enables smaller feature size. The latter is aresult of fewer lithography steps, which require an offset toaccommodate misalignment.

The thinner deposition on the sidewalls in each of LED 200 and LED 400leverage the thinner deposition on sidewall to create an energy barrierby increasing bandgap (thinner QWs) on sidewall epitaxial layers,increase electrical resistance to current spreading (thinner P-layer),reduce sidewall recombination by blocking hole current flow, improveefficiency by isolating current injection to light emitting region ontop of mesa, and reduce processing and fabrication cost.

In an exemplary embodiment, a micrometer scale light emitting diode(uLED) comprises: a plurality of continuous epitaxial layers comprising:a n-layer having a first flat region, a sloped region, and a second flatregion; an active layer adjacent to the first flat region of the n-layerand a portion of the sloped region of the n-layer; a p-layer adjacent tothe first flat region of the active-layer and a portion of the slopedregion of the n-layer; a thickness of the n-layer in sloped region beingless than a thickness of the n-layer in the first flat region or thesecond flat region or both; and the active layer, or the p-layer, orboth the active and p-layers comprise a pinch-off zone within the slopedregion; a p-contact on the p-layer adjacent to the first flat region;and an n-contact on the n-layer adjacent to the second flat region. TheuLED may include one or more of the following: an absence of apassivation layer on the sloped region; thickness of the n-layer in thesloped region is less than 80% of the thickness of the n-layer in thefirst flat region or the second flat region or both; thickness of theactive layer adjacent to the portion of the sloped region of the n-layeris less than 80% of the thickness of the active layer adjacent to thefirst flat region of the n-layer; thickness of the p-layer adjacent tothe portion of the sloped region of the n-layer is less than 80% of thethickness of the p-layer on the first flat region of the n-layer; anangle created by the first flat region and the sloped region is between45 degrees and 160 degrees; the first flat region is verticallydisplaced from the second flat region by a distance; the distance isbetween 1 μm and 10 μm; at least one layer of light converting phosphoradjacent to the n-layer; at least one characteristic dimension of lessthan 100 micrometers, the character dimension being selected from thegroup consisting of: height, width, depth, thickness, and combinationsthereof; a body on which the plurality of continuous epitaxial layers isdeposited; the body may be: sapphire, silicon, silicon carbide, GaN, orGaAs.

In an exemplary embodiment, a micrometer scale light emitting diode(uLED) comprises: a substrate comprising: a first flat region, a secondflat region parallel to the first flat region, a sloped sidewallconnecting the first flat region and the second flat region; a pluralityof continuous epitaxial layers on the substrate comprising: a n-layer onthe entirety of the substrate; an active layer adjacent to a portion ofthe n-layer; a p-layer adjacent to a portion of the active layer; athickness of the n-layer on the sloped sidewall being less than athickness of the n-layer on the first flat region or the second flatregion or both; and the active layer, or the p-layer, or both the activeand p-layers comprise a pinch-off zone within the sloped region; ap-contact on the p-layer adjacent to the first flat region; and ann-contact formed on the n-layer adjacent to the second flat region. TheuLED may include one or more of the following: an absence of apassivation layer on the sloped sidewall; thickness of the n-layer inthe sloped sidewall is less than 80% of the thickness of the n-layer inthe first flat region or the second flat region or both; thickness ofthe active layer adjacent to the portion of the sloped sidewall of then-layer is less than 80% of the thickness of the active layer adjacentto the first flat region of the n-layer; thickness of the p-layeradjacent to the portion of the sloped sidewall of the n-layer is lessthan 80% of the thickness of the p-layer on the first flat region of then-layer; an angle created by the first flat region and the slopedsidewall is between 45 degrees and 160 degrees; the first flat region isvertically displaced from the second flat region by a distance; thedistance is between 1 μm and 10 μm; at least one layer of lightconverting phosphor adjacent to the n-layer; at least one characteristicdimension of less than 100 micrometers, the character dimension beingselected from the group consisting of: height, width, depth, thickness,and combinations thereof; the substrate may be: sapphire, silicon,silicon carbide, GaN, or GaAs.

Examples of layouts for minimizing footprint and maximizing performanceand manufacturability are shown in FIGS. 9-18. The light-emitting mesasmay be square, rectangular or other types of polygons. The p-contact istypically the largest of the two contacts since the light generation andactive region current injection occur principally under the p-contact. Alarger p-contact reduces current density and improves efficiency formost operating currents. The size of the n-contact may be smaller tominimize footprint, however an n-contact around the entire perimeterwould reduce the current density and electric field in the sidewallregions, minimizing leakage current and operating voltage.

FIGS. 5A-L (collectively referred to as FIG. 5) illustrate a monolithicLED array (e.g., Thin Film Flip Chip (TFFC)) 500 at various stages ofthe workflow and the accompanying FIG. 6A represents the method 600 ofmanufacturing a monolithic LED array (e.g., TFFC). As shown in FIG. 5,an array of LEDs, e.g., uLEDs, may be generated and each LED may includea first flat region, a second flat region recessed from the first flatregion, and slopped sidewalls that connect the first flat region to thesecond flat region. Notably, epitaxial layers of the sloped sidewallscomprise pinch-off zones in that they have thicknesses less than theircorresponding thicknesses on the flat regions. In one or moreembodiments, the epitaxial layers in/of the sloped sidewalls may have athickness that is less than 80% of their corresponding thickness in/ofthe first flat region and/or second flat region. For a given dopinglevel, the electrical resistance of the p-layer is inverselyproportional to the layer thickness, thus the reduction of thickness ofthe p-layer in the sloped region increases electrical resistance andreduces parasitic hole leakage currents between the first portion andthe second or slopped sidewalls. For example, a 50% reduction inthickness may increase the resistance by 200% and reduce parasitic holecurrents by a factor of 2. Similar reduction of the thickness of the QWactive region in the sloped sidewalls will increase the energy bandgapof the crystal in that region. The higher energy bandgap will create anenergy barrier and confine carriers to the first region. For example, a50% decrease in QW thickness would increase the energy bandgap by ˜75meV and provide effective confinement. A second effect of the thinner QWactive region is to increase the forward voltage of the p-n junction inthe sloped sidewalls. Parasitic hole currents that flow from the firstregion to the sloped sidewalls will be blocked from flowing through thep-n junction in the sloped sidewalls. The combined effect of thinnerp-layer and QW active region in the sloped sidewalls may effectivelycause greater than 90% of a forward bias hole injection to be confinedto the first flat portion of an LED.

FIGS. 5 and 6A are discussed in parallel to describe the method ofmanufacturing a monolithic LED array, e.g., a thin film flip chip(TFFC), and the associated depictions of the monolithic LED array ateach stage of the method. The array of LEDs created in accordance withFIG. 5 and FIG. 6A may include, for example, several million uLEDsconfigured to provide a complete high density RGB display or,alternatively, three to five LEDs that are configured as a full colorgamut pixel (e.g., configured to emit the entire range of colorsavailable on a particular device such as a mobile phone, a monitor, orthe like). Alternatively, the array of LEDs created in accordance withFIG. 5 and FIG. 6A may be a single color monolithic micro display (e.g.,a red, a green, or a blue) such that all or a group of LEDs in the arrayeach emit the same color.

Method 600 includes the formation of a patterned body (e.g., substrateor template) at 601. For illustration purposes, reference is made to apatterned substrate. As shown in FIG. 5A, patterned substrate 505 may beformed with a pattern (generally shown in FIG. 5A) including height h,width w, street width s, number of steps n and angle φ to achieve adesired shape as discussed above with respect to FIGS. 2A-2B, 3, and 4.

At 602 of method 600, the epitaxial growth may be formed having adesired emission wavelength, for example, ranging from infrared toultraviolet. In an example, a near-UV emission wavelength is desired. Asshown in FIG. 5B, the epitaxy may include an n-layer 510, an activelayer 515, and a p-layer 520. Each of these layers may be as describedwith respect to FIG. 4 and may be formed using a technology such asorganometallic vapor-phase epitaxy (OMVPE), and/or metalorganic vapordeposition (MOCVD), for example. FIGS. 6B and 6C show exemplary methodsof generating light emitting devices (LEDs) having epitaxy layers.

At 603 of method 600, a resist 506 may be applied to the structure. Asshown in FIG. 5C, a resist 506 may be applied adjacent to the p-layer520. Resist 506 may include a pattern in preparation for subsequentsteps in method 600.

At 605 of method 600, the epi layer (including n-layer 510, active layer515, p-layer 520) may be etched to provide access to substrate 505. Then-contact metals may be applied at 610 and may be applied by anyapplicable manner such as by deposition. As shown in FIG. 5D, n-contacts530 may be electrically coupled to the substrate 505 based on theetching and deposition. The n-contacts 530 may entirely surround eachLED to provide for optical isolation and/or optical reflection of eachLED, and may also minimize operating voltage.

At 615 of method 600, a subsequent resist layer 508 may be applied ontop-layer 520 surrounding the exposed n-contact 530. Resist layer 508 maybe patterned in order to provide for the subsequent placement of ap-contact layer. In FIG. 5E, resist layer 508 is formed to provide anopportunity for the subsequent placement of a p-contact.

At 620 of method 600, p-contact metals may be deposited by anyapplicable techniques such as by a lift-off deposition. As illustratedin FIG. 5F, p-contacts 525 may be placed adjacent to p-layer 520. Asshown, the wafer may be singulated at step 621 after the p-contactmetals are deposited at 620. According to embodiments, if step 621 isnot taken after step 620, then the wafer may be singulated after anysteps 625-650 of FIG. 6a . The singulation may result in a single pixel(e.g., red, green, blue LEDs) or larger groups of LEDs to create anarray.

At 625 and referring to FIG. 5G, the structure may be bonded to abackplane such as the TFT backplane 585 (e.g., a Si TFT backplane). TFTbackplane 585 may be coupled to p-contact 525 and n-contact 530 toprovide the control and electrical connections to the LED. TFT backplane585 may be a MOSFET or amorphous Si CMOS, for example. The backplane maybe configured to individually address each of a plurality of LEDs in anarray of LEDs.

At 630 of method 600, additional optical isolation and/or reflection maybe provided by injecting a TiOx-silicone underfill 512 to fill in areasaround n-contact 530, p-contact 525 and p-layer 520. Underfill 512 maybe worked back to expose bonding metal of the contacts, p-contact 525and n-contact 530. As illustrated in FIG. 5H, underfill 512 may form acomplete structure. TiOx-silicone underfill 512 provides mechanicalstrength, chemical protection, optical isolation and reflectivity. Asshown in FIG. 5H, the n-contacts 530 may extend through the n-layer 510to the substrate 505. According to another embodiment (not shown), then-contacts may extend into the n-layer 510 but not through the n-layer510.

At 635 and as depicted in FIG. 5I, the structure may be inverted and thegrowth substrate 505 may be removed. FIG. 5I is a cross section of FIG.5L at the cross line C, and as further disclosed herein. Once removed,n-layer 510 may be exposed. The removal of the growth substrate 505 maycreate pockets such that a first flat region of the structure is a baseof the pocket and the sloped sidewalls of each structure create thesides of the pocket. As further disclosed herein, the pockets may befilled with phosphors 514. The phosphors 514 may all be the samespectral properties for each created LED or different LEDs (e.g.,adjacent LEDs) may include different phosphor particles with differentspectral properties such that the light emission from such differentphosphor particles is different across a set of LEDs. According to anembodiment, an array of LEDs may include a plurality of LEDs that form aRGB display for projection of full color images based at least ondifferent phosphor material deposited in or on a set of LEDs.Alternatively, the pockets may be filed with a high refractive indexmaterial, such as in the case of a single color monolithic array. As anexample, the high refractive index may have a refractive index greaterthan 1.5. The structure may include n-layer 510, active layer 515 andp-layer 520, with p-contacts 525 and n-contacts 530 each attached to TFTbackplane 585. Although not specifically illustrated in FIG. 5, asubmicron patterning of the exposed semiconductor may occur at 640. Then-contacts 530 may have a height such that they optically isolate twoadjacent LEDs. As shown in FIG. 5I, the epitaxial layers may include afirst flat region 510 a, sidewalls 510 b and second flat region 510 c.

At 645 and as depicted in FIG. 5J, phosphors 514 may be deposited ontonewly exposed n-layer 510 to convert NUV (e.g., approximately 400 nmwavelength), blue (e.g., royal blue at approximately 450 nm), or likelight to the desired color emission. The structure may include phosphors514, n-layer 510, active layer 515 and p-layer 520, with p-contacts 525and n-contacts 530 each attached to TFT backplane 585. Phosphors 514 maybe selected to produce colors such as blue, green and red, for example.A silicone encapsulant and/or an epoxy encapsulant may be provided onthe phosphors 514.

At 650 and as depicted in FIG. 5K, optical elements 550 may be added tobe optically coupled to phosphors 514. These optical elements 550 may bedesigned to collimate the emission from phosphors 514, for example.Alternatively, optical elements 550 may be used to manipulate theemitted radiation from phosphors 514 or through high refractive indexmaterial (e.g., material with a refractive index greater than 1.5) inothers ways, such as focusing, for example. As noted herein, then-contacts 530 may optically isolate emissions from two adjacent opticalelements 550 such that emissions from a first optical element of opticalelements 550 does not enter or otherwise interfere with the emissionfrom an adjacent optical element of the optical elements 550 in anadjacent LED.

For completeness, the bottom of the array of LEDs is shown in FIG. 5L.The pattern is looking down on FIG. 5I after the removal of patternedsubstrate 505. N-contact 530 is shown. N-contact 530 is adjacent tofirst flat region 510 a which surrounds the sloped sidewalls 510 b. Thefirst flat region 510 a and sloped sidewalls 510 b are shown to surroundthe second flat region 510 c. Notably, the n-contact 530 may bepositioned and/or have a height that results in optical isolationbetween two adjacent LEDs.

With the techniques herein, no pixel level singulation is required, sothe loss in area associated with scribe streets is avoided. A lateraln-contact may be used to maximize the available light emitting area fora given pitch. The contact metal may extend upwards far enough toprovide optical isolation and a “pocket” for phosphor deposition.Alternate methods of enhancing reflection may include providing aninorganic reflector on the non-contact areas of the device. Techniquesinclude physical vapor deposition of dielectric and metal coatings, aswell as atomic layer deposition of reflector layers. The preciseregistration of the patterned substrate may enable phosphor depositiontechniques. For example, in an embodiment, quantum dot printingtechniques, such as intaglio transfer printing may be used. Othertechniques such as, but not limited to, screen printing or micro-moldingmay also be used to enable the claimed LED device form factors.

The display may be monochrome, built from a single color (ultra-violet,violet, blue, green, red, or infra-red) emitting wafer or a multi-colorarray built by adding converters such as phosphors and quantum dots toconvert the pump light into various color pixels. A combination ofdirect and PC converted light with three or more colors may be utilized.The size or number of a given color pixel may be adjusted to optimizeperformance, for example, a large green pixel plus blue and red, or twosmall green pixels plus blue and red. The present disclosure may removethe requirement of the pick and place process relieving a major sourceof cost that currently hinders commercialization. It should be notedthat the method of FIG. 6A may be modified to fabricate individual red,green, and blue LEDs that are picked and placed in a display device. Then-contact may be made discontinuous to create appropriate scribe streetsand the pixels laid out in regular grid. Singulation may occur before640 of method 600.

FIG. 6D shows a process similar to FIG. 6A however instead of apatterned substrate, an n-Gan pattern may be formed at step 661.Remaining epitaxial layers (e.g., p-layer, n-growth or regrowth layer,and active layer) may be grown at step 662. A resist may be applied atstep 663, as described in step 600 of FIG. 6A. A pattern may be etchedthrough the p-layer and active layer to expose the n-layer at step 663.N-contact metals may be formed at step 665, and resist may be appliedand patterned at step 665. P-contact metals may be formed at step 666and the wafer may be singulated into a smaller group of LEDs at step667. It will be understood that the details provided in accordance withFIG. 6A may apply to one or more of the steps recited in FIG. 6D.

FIG. 6B includes a method 680 for producing light emitting devices(LEDs) having epitaxial layers. The LEDs may be generated as a waferthat may be singulated to provide an array of LEDs that may beimplemented in a display device such as a color display. At 681 apatterned substrate having mesas with bottom surfaces and slopedsidewalls extending from the bottom surfaces towards a non-patternedsurface of the patterned substrate may be provided. FIG. 5F shows anexample of first flat regions that are adjacent to p-contacts 525,second flat regions that are in contact with n-contacts 530, and slopedsidewalls that connect the first flat regions to the second flatregions.

In an exemplary embodiment, a method for manufacturing a monolithiclight emitting diode (LED) array comprises: growing an epitaxial layeran active layer and a p-layer on a patterned body, the patterned bodycomprising a patterned substrate and a continuous epitaxial n-layer, ora patterned n-layer on a planar substrate. The patterned body comprisesa first plurality of flat regions comprising a first crystallographicplane orientation and being located a first distance from a base of thepatterned body, a second plurality of flat regions comprising the firstcrystallographic plane orientation and being located a second distancefrom a base of the patterned body, the second distance being smallerthan the first distance, and a plurality of sloped sidewalls comprisinga second crystallographic plane orientation, such that a portion of then-layer positioned adjacent to the sloped sidewalls has a thickness lessthan a thickness of portions of the n-layer adjacent any of the flatregions. A first resist is applied to the epitaxial layer adjacent tothe p-layer, the resist being patterned to provide access to thepatterned substrate or the planar substrate. N-contact metals aredeposited to produce n-contacts electrically coupled to the patternedsubstrate or the planar substrate. A second resist is applied to theepitaxial layer, the second resist being designed for placement ofp-contacts. P-contact metals are deposited to produce the p-contactselectrically coupled to the p-layer to form a plurality of lightemitting diodes (LEDs). A thin film transistor (TFT) is bonded backplaneto the plurality of LEDs, the bonding causing the p-contacts andn-contacts to provide the electrical connections to the LEDs. Anunderfill is injected to fill in areas surrounding the p-contacts,n-contacts, and p-layer. The patterned substrate or the planar substrateis removed and the n-layer is exposed, thereby forming a thin film flipchip (TFFC) array. The method may further comprise one or more of:submicron patterning of exposed n-layer; depositing n-contact andoptical isolation metals in electrical contact to the n-layer;depositing a phosphor layer onto the exposed n-layer; and adding opticalelements optically coupled to the phosphor layer.

As disclosed herein, one or more epitaxial layers may be grown ondifferent portions of a patterned substrate or n-layer. The differencein growth rates between different flat portions (e.g., first flatportion and second flat portion) may be achieved based on differences inheight between the layers, due to the respective distances a reactantdiffuses through to reach a given flat layer. For example, a reactantmay travel a greater distance to reach a bottom layer than a top layer,resulting in different growth rates. Additionally, differences in growthrates between flat portions (e.g., first flat portion and second flatportion) and the sloped sidewalls may be achieved due to differences insurface energy that affect surface diffusion and kinetics. Notably, thesurface orientation of a sloped sidewall may result in a change ingrowth rate as a reactant may bond with the sloped surface at an anglewhich affects the bonding process due to the slope. Additionally, thegrowth rates between surfaces may be affected based on the moleculeorientation of the respective crystallographic planes of the layers. Forexample, an C-crystallographic plane orientation may allow for a fastergrowth rate in comparison to an A-crystallographic plane orientation orM-crystallographic plane orientation.

At 685, a continuous n-layer, active layer, and p-layer having a firstregion may be grown over the non-patterned surfaces, a second regionover the bottom surface, and a third region over the sloped sidewalls,the third region of the n-layer, active layer, and p-layer having aslower growth rate than the growth rate of the first and second regionsof the n-layer, active layer, and p-layer, respectively. The angle ofthe sloped sidewalls and/or the crystallographic plane orientation maybe modified to adjust the growth rate of a given region or sidewall. Forexample, the crystallographic plane orientation of the sloped sidewallsmay result in slower growth rate when compared to the crystallographicplane orientation of the first flat region and/or second flat region.FIG. 10A includes a patterned substrate growth substrate 1005. Asemiconductor in accordance with method 680 may be grown on thepatterned substrate growth substrate 1005, resulting in the LED 1000.

Epitaxial layers in the sloped sidewall may have a thickness that isless than 80% of their corresponding thickness in the first flat portionand/or second flat portion. For a given doping level, the electricalresistance of the p-layer is inversely proportional to the layerthickness, thus the reduction of thickness of the p-layer in the slopedregion increases electrical resistance and reduces parasitic holeleakage currents between the first portion and the second portion orsloped sidewalls. For example, a 50% reduction in thickness mayincreases the resistance by 200% and reduce parasitic hole currents by afactor of 2. Similar reduction of the thickness of the QW active regionin the sloped sidewalls will increase the energy bandgap of the crystalin that region. The higher energy bandgap will create an energy barrierand confine carriers to the first region. For example, a 50% decrease inQW thickness may increase the energy bandgap by ˜75 meV and provideeffective confinement. A second effect of the thinner QW active regionis to increase the forward voltage of the p-n junction in the slopedsidewalls. Parasitic hole currents that flow from the first region tothe sloped sidewalls will be blocked from flowing through the p-njunction in the sloped sidewalls. The combined effect of thinner p-layerand QW active region in the sloped sidewalls may effectively causegreater than 90% of a forward bias hole injection to be confined to thefirst flat region of an LED.

FIG. 6C includes a method 690 for producing light emitting devices(LEDs) having epitaxy layers. The LEDs may be generated as a wafer thatmay be singulated to provide an array of LEDs that may be implemented ina display device such as a color display. At 691 of method 690, ann-layer having mesas with un-patterned surfaces and sloped sidewallsextending from the un-patterned surfaces towards a bottom surface of thepatterned substrate may be provided. The n-layer may be grown over apatterned substrate or may be grown and shaped using any applicableshaping process such as via lithography. FIG. 3 shows an example offirst flat regions that are adjacent to p-contacts 325, second flatregions that are in contact with n-contacts 330, and sloped sidewallsthat connect the first flat regions to the second flat regions.

At 695, a continuous active layer, and p-layer (and, optionally, ngrowth or regrowth layer) having a first region over the non-patternedsurfaces, a second region over the bottom surface, and a third regionover the sloped sidewalls, the third region of the n-layer, activelayer, and p-layer having a slower growth rate than the growth rate ofthe first and second regions of the n-layer, active layer, and p-layer,respectively. The angle of the sloped sidewalls and/or thecrystallographic plane orientation may be modified to adjust the growthrate of a given region or sidewall. For example, the crystallographicplane orientation of the sloped sidewalls may result in slower growthrate when compared to the crystallographic plane orientation of thefirst flat region and/or second flat region. FIG. 10B includes a shapedn-layer 1011. A semiconductor structure in accordance with method 690may be grown on the n-layer 1011, resulting in the LED 1001.

FIGS. 7A-7I (collectively referred to as FIG. 7) illustrate a monolithicLED array (e.g., Vertical Injection Thin Film (VTF)) 700 at variousstages of the workflow, and the accompanying FIG. 8 represents themethod 800 of manufacturing a monolithic LED array (e.g., VTF). Asshown, the monolithic LED array 700 includes a plurality of LEDs andeach LED may include a first flat region, a second flat region recessedfrom the first flat region, and sloped sidewalls that connect the firstflat region to the second flat region. Notably, the epitaxial layers inthe sloped sidewalls may have a thickness that is less than 80% of theircorresponding thickness in the first flat region and/or second flatregion. For a given doping level the electrical resistance of thep-layer is inversely proportional to the layer thickness, thus thereduction of thickness of the p-layer in the sloped region increaseselectrical resistance and reduces parasitic hole leakage currentsbetween the first region and the second region or sloped sidewalls. Forexample, a 50% reduction in thickness may increase the resistance by200% and reduce parasitic hole currents by a factor of 2. Similarreduction of the thickness of the QW active region in the slopedsidewall will increase the energy bandgap of the crystal in that region.The higher energy bandgap will create an energy barrier and confinecarriers to the first region. For example, a 50% decrease in QWthickness may increase the energy bandgap by ˜75 meV and provideeffective confinement. A second effect of the thinner QW active regionis to increase the forward voltage of the p-n junction in the slopedsidewalls. Parasitic hole currents that flow from the first region tothe sloped sidewalls will be blocked from flowing through the p-njunction in the sloped sidewalls. The combined effect of thinner p-layerand QW active region in the sloped sidewalls may effectively causegreater than 90% of a forward bias hole injection to be confined to thefirst flat region of an LED.

FIGS. 7 and 8 are discussed in parallel to describe the method ofmanufacturing of a monolithic LED array (VTF) and the associateddepictions of the monolithic LED array at each stage of the method.FIGS. 7 and 8 illustrate the process workflow and method for amonolithic LED display using the VTF architecture with n- and p-contactson opposite sides of the epitaxial layers (phosphor deposition andoptional optical element attachment steps not shown). The array of LEDscreated in accordance with FIG. 7 and FIG. 8 may include, for example,several million LEDs configured to provide a complete high density RGBdisplay or, alternatively, three to five LEDs that are configured as afull color gamut pixel (e.g., configured to emit an entire range ofcolors available on a particular device such as a mobile phone, amonitor, or the like).

Method 800 includes the formation of a patterned substrate at 805. Asshown in FIG. 7A, patterned substrate 705 may be formed with a pattern(generally shown in FIG. 7A) including height h, width w, street widths, number of steps n and angle φ to achieve desired shape as discussedabove with respect to FIGS. 2A-2B, 3, and 4.

At 810 of method 800, the epitaxial growth may be formed having adesired emission wavelength, for example, ranging from infrared toultraviolet. In an example, a near-UV emission wavelength. As shown inFIG. 7B, the epitaxy may include an n-layer 710, an active layer 715,and a p-layer 720. Each of these layers may be as described with respectto FIG. 4 and may be formed using a technology such as organometallicvapor-phase epitaxy (OMVPE), and/or metalorganic vapor deposition(MOCVD), for example. FIGS. 6B and 6C show exemplary methods ofgenerating light emitting devices (LEDs) having epitaxy layers

At 815 of method 800, a resist 706 may be applied to the structure. Asshown in FIG. 7C, resist 706 may be applied adjacent to the p-layer 720.Resist 706 may include a pattern in preparation for subsequent steps inmethod 800. It will be noted that although resist 706 is shown as ahexagon, the shape of the resist 706 may match the shape of thep-contacts 725 (e.g., FIG. 7D) such that the resist 706 is shaped toallow formation of the corresponding p-contacts 725.

At 820 of method 800, p-contact metals 725 and an alloy may be formed byany applicable technique such as via deposition. As illustrated in FIG.7D, p-contacts 725 may be placed adjacent to p-layer 720.

At step 825 and referring to FIG. 7E, the structure may be bonded to thethin film transistor (TFT) backplane 785. TFT backplane 785 may becoupled to p-contact 725 to provide the control and electricalconnections to the LED. TFT backplane 785 may be a MOSFET or amorphousSi CMOS for example.

At 830 of method 800, the structure is injection filled with aTiOx-silicone underfill 712 to fill in areas around p-contact 725 andp-layer 720. Underfill 712 may be worked back to expose bonding metal ofp-contact 525. As illustrated in FIG. 7F, underfill 712 may form acomplete structure. TiOx-silicone underfill 712 provides mechanicalstrength, chemical protection, optical isolation and reflectivity.Alternatively, for greater optical isolation between LEDs, inorganiclayers with alternating high and low refractive index may be depositedover p-layer 715 via a lift-off process.

At 835 and as depicted in FIG. 7G, the structure may be inverted and thegrowth substrate 705 may be removed. Once removed, n-layer 710 may beexposed. The removal of the growth substrate 705 may create pockets suchthat a first flat region of the structure is a base of the pocket andthe sloped sidewalls of each structure create the sides of the pocket.The structure may include n-layer 710, active layer 715 and p-layer 720,with p-contacts 725 attached to TFT backplane 785. Although not shown inFIG. 7, 840 may include submicron patterning of the exposedsemiconductor.

At 845 of method 800, a resist 708 may be applied to the structure andmay create gaps 709. As shown in FIG. 7G, resist 708 may be appliedadjacent to the n-layer 710. Resist 708 may include a pattern inpreparation for subsequent steps in method 800.

At 850 of method 800, the epitaxial layer is etched to the contactlayer. At 855 of method 800, a metal stack may then be deposited toprovide the n-contact 730. As shown in FIG. 7H, n-contacts 730 may beelectrically coupled to n-layer 710 based on the etching and deposition.As shown, phosphor material 795, 796, and 797 may be provided inrespective different LEDs and may be the same phosphor material ordifferent phosphor material with different spectral properties. Althoughnot shown in FIG. 7, 855 includes depositing n-contact and opticalisolation materials. The n-contacts 730 may optically isolate twoadjacent LEDs such that emission from a first LED may not enter orotherwise optically interfere with emissions from a second adjacent LED.FIG. 7H shows a cross section of FIG. 7I at the cross line D, as shown.

At 860 of method 800, phosphors (not shown—see FIG. 5) may be depositedonto the exposed n-layer to convert NUV (e.g., approximately 400 nmwavelength), blue (e.g., royal blue at approximately 450 nm), or likelight to the desired color emission. Phosphors 514 may be selected toproduce colors such as blue, green and red, for example. As shown, thewafer may be singulated at step 861 after the phosphor is deposited at860. According to embodiments, the wafer may be singulated at othersteps such as after step 820 or any steps of FIG. 8 shown thereafter.

At 865 of method 800, optional optical elements (not shown—see FIG. 5)may be added to be optically coupled to phosphors. These opticalelements may be designed to collimate the emission from phosphors, forexample. Alternatively, optic elements may be used to manipulate theemitted radiation from phosphors in others ways, such as focusing, forexample.

For completeness, the top of the array of LEDs is shown in FIG. 7I. Thepattern is looking down on FIG. 7H. N-contact 730 is shown. N-contact730 is adjacent to the a plurality of LEDs including LED 790 which emitsred light, LED 791 which emits green light, and LED 792 which emits bluelight. Notably, the n-contact 730 may be positioned and/or have a heightthat results in optical isolation between two adjacent LEDs such asbetween LED 790 and LED 791.

All the capabilities described above for the flip chip version of themonolithic array are applicable to the VTF version, with the exceptionof the fabrication of individual elements. Individual VTF emitters areunlikely to be competitive with flip-chip elements.

In an exemplary embodiment, a method for manufacturing a monolithiclight emitting diode (LED) array comprises: growing an epitaxial layerincluding an active layer and a p-layer on a patterned body, thepatterned body comprising a patterned substrate and a continuousepitaxial n-layer, or a patterned n-layer on a planar substrate, a firstplurality of flat regions comprising a first crystallographic planeorientation and being located a first distance from a base of thepatterned substrate, a second plurality of flat regions comprising thefirst crystallographic plane orientation and being located a seconddistance from a base of the patterned body, the second distance beingsmaller than the first distance, a plurality of sloped sidewallscomprising a second crystallographic plane orientation, and a portion ofthe n-layer positioned adjacent to the sloped sidewalls having athickness less than a thickness of portions of the n-layer adjacent anyof the flat regions; applying a first resist to the p-layer, the firstresist being patterned to provide access to a portion of the p-layer;depositing p-contact adjacent to the p-layer to form a plurality oflight emitting diodes (LEDs); bonding to a thin film transistor (TFT)backplane to form a plurality of light emitting diodes (LEDs), thebonding causing the p-contacts to provide the electrical connections tothe LEDs; injecting an underfill to fill in areas surrounding thep-contacts, n-contacts, and p-layer; removing the patterned substrate orplanar substrate by inverting the manufactured structure to expose then-layer thereby forming a vertical injection thin film (VTF) array. Themethod may further comprise one or more of: submicron patterning ofexposed n-layer; depositing n-contact and optical isolation metals inelectrical contact to the n-layer; depositing a phosphor layer onto theexposed n-layer; and adding optical elements optically coupled to thephosphor layer.

Both methods 600 and 800 are compatible with standard TFT backplanes toenable compatibility with existing systems. Methods 600 and 800 offerthe potential for a flexible display if mated to a flexible backplane.Optical isolation between pixels of both pump and converted light isexcellent. Coupling of optical elements may be done in an efficientparallel fashion with, for example, over-molding.

The various embodiments are depicted in the non-exclusive illustrationsof FIGS. 9-22.

FIG. 9 illustrates a LED 900 created by growth/regrowth on a patternedn-layer 910 with a subsequent device growth. While LED 900 includes acircular cross-section, LEDs may be configured based on LED 900 withother cross sections. LED 900 includes a layered device including layersof a substrate 905, n-layer 910, n-layer growth/regrowth 965, activelayer 915, electron blocking layer (EBL) 935, p-layer 920, and p-contact925. EBL 935 may provide electron blocking as would be understood in theart and/or may provide a set-back in the geometry of the configuration.N-contact 930 may be provided around the layered device and may extendas high or low on the device structure as needed to provide thenecessary electrical connections. LED 900 may be formed via method 600.LED 900 is depicted before removal of the substrate 905 in method 600.As shown in FIG. 9, the epitaxial layers each include a flat firstregion and a sloped sidewall region. The n-layer 910 also includes asecond flat region in contact with the n-contact 930. The slopedsidewall region is shown to be etched to a width that creates apinch-off region as disclosed herein. According to an embodiment, asshown in FIG. 9, the second flat region only includes the n-layer 910such that growth of other epitaxial layers does not extend to the secondflat region.

FIG. 10A illustrates a LED 1000 created on a patterned substrate 1005.While LED 1000 includes a circular cross-section, LEDs may be configuredbased on LED 1000 with other cross sections. LED 1000 includes a layereddevice including epitaxial layers of a substrate 1005, n-layer 1010,active layer 1015, EBL 1035, p-layer 1020, and p-contact 1025. EBL 1035may provide electron blocking as would be understood in the art and/ormay provide a set-back in the geometry of the configuration. N-contact1030 may be provided around the layered device and may extend as high orlow on the device structure as needed to provide the necessaryelectrical connections and/or optical isolation between adjacent LEDs1000 in an array of LEDs. LED 1000 may be formed via method 600 of FIG.6B and/or 680 of FIG. 6C. LED 1000 is depicted before removal of thesubstrate 1005 in method 600. As shown in FIG. 10A, the epitaxial layerseach include a flat first portion and a sloped sidewall portion. Thesloped sidewall region is shown to be etched or grown to a width thatcreates a pinch-off region as disclosed herein. Notably, the contactplacement of the n-contact 1030 and p-contact 1025 and the material growto form the epitaxial layers minimizes carrier transport to the slopedsidewall and/or edges of the active layer 1015.

In an exemplary embodiment, a method for manufacturing a monolithiclight emitting diode (LED) array comprising a plurality of micro-lightemitting diodes (uLEDs) comprising a plurality of epitaxial layerscomprises: epitaxially depositing an n-layer on a patterned substrate,the patterned substrate comprising a first plurality of flat regionscomprising a first crystallographic plane orientation and being locateda first distance from a base of the patterned substrate, a secondplurality of flat regions comprising the first crystallographic planeorientation and being located a second distance from a base of thepatterned substrate, the second distance being smaller than the firstdistance, a plurality of sloped sidewalls comprising a secondcrystallographic plane orientation, and a portion of the n-layerpositioned adjacent to the sloped sidewalls having a thickness less thana thickness of portions of the n-layer adjacent any of the flat regions;epitaxially depositing an active layer on an area of the n-layeradjacent to the first plurality of flat regions and adjacent to thesloped sidewalls, such that a portion of the active layer positionedadjacent to the sloped sidewalls has a thickness less than a thicknessof the portion of the active layer adjacent to the first plurality offlat regions; epitaxially depositing a p-layer on an area of the activelayer adjacent to the first plurality of flat regions and adjacent tothe sloped sidewalls, such that a portion of the p-layer layerpositioned adjacent to the sloped sidewalls has a thickness less than athickness of the portion of the p-layer adjacent to the first pluralityof flat regions; forming a plurality of p-contacts on the portion of thep-layer adjacent to the first plurality of flat regions; and forming aplurality of n-contacts on the portion of the n-layer adjacent to thesecond plurality of flat regions, whereby the plurality of uLEDs isformed. This method may be performed in an absence of any sidewallpassivation. Methods may further comprise one or more of: bonding theplurality of uLEDs to a thin film transistor (TFT) backplane, removingthe patterned substrate; depositing a phosphor layer onto an exposedsurface of the n-layer; adding optical elements optically coupled to thephosphor layer. When the p-contact and the n-contact are formed on thesame side of the epitaxial layers, a thin film flip chip (TFFC) array isformed. When the p-contact and the n-contact are formed on oppositesides of the epitaxial layers, a vertical injection thin film (VTF)array is formed.

In an exemplary embodiment, a method for manufacturing a monolithiclight emitting diode (LED) array comprising a plurality of micro-lightemitting diodes (uLEDs) comprising a plurality of epitaxial layerscomprises: forming a patterned template comprising an n-layer on asubstrate, the patterned template comprising a first plurality of flatregions comprising a first crystallographic plane orientation and beinglocated a first distance from a base of the substrate, a secondplurality of flat regions comprising the first crystallographic planeorientation and being located a second distance from a base of thesubstrate, the second distance being smaller than the first distance, aplurality of sloped sidewalls comprising a second crystallographic planeorientation, and a portion of the n-layer positioned adjacent to thesloped sidewalls having a thickness less than a thickness of portions ofthe n-layer adjacent any of the flat regions; epitaxially depositing anactive layer on an area of the n-layer adjacent to the first pluralityof flat regions and adjacent to the sloped sidewalls, and a portion ofthe active layer positioned adjacent to the sloped sidewalls having athickness less than a thickness of the portion of the active layeradjacent to the first plurality of flat regions; epitaxially depositinga p-layer on an area of the active layer adjacent to the first pluralityof flat regions and adjacent to the sloped sidewalls, and a portion ofthe p-layer layer positioned adjacent to the sloped sidewalls having athickness less than a thickness of the portion of the p-layer layeradjacent to the first plurality of flat regions; forming a plurality ofp-contacts on the portion of the p-layer adjacent to the first pluralityof flat regions; and forming a plurality of n-contacts on the portion ofthe n-layer adjacent to the second plurality of flat regions, wherebythe plurality of uLEDs is formed. This method may be performed in anabsence of any sidewall passivation. Methods may further comprise one ormore of: bonding the plurality of uLEDs to a thin film transistor (TFT)backplane, removing the patterned substrate; depositing a phosphor layeronto an exposed surface of the n-layer; adding optical elementsoptically coupled to the phosphor layer. When the p-contact and then-contact are formed on the same side of the epitaxial layers, a thinfilm flip chip (TFFC) array is formed. When the p-contact and then-contact are formed on opposite sides of the epitaxial layers, avertical injection thin film (VTF) array is formed.

FIG. 10B illustrates a LED 1001 created on a patterned substrate 1006and shaped n-layer 1011. While LED 1001 includes a circularcross-section, LEDs may be configured based on LED 1001 with other crosssections. LED 1001 includes a layered device including epitaxial layersof a substrate 1006, shaped n-layer 1011, re-grown n-layer 1012, activelayer 1016, EBL 1036, p-layer 1021, and p-contact 1026. The shapedn-layer 1011 may be shaped by any applicable shaping process such aslithography. EBL 1036 may provide electron blocking as would beunderstood in the art and/or may provide a set-back in the geometry ofthe configuration. N-contact 1031 may be provided around the layereddevice and may extend as high or low on the device structure as neededto provide the necessary electrical connections and/or optical isolationbetween adjacent LEDs 1001 in an array of LEDs. LED 1000 may be formedvia method 600 of FIG. 6B and/or 690 of FIG. 6C. LED 1000 is depictedbefore removal of the substrate 1006 in method 600. As shown in FIG.10B, the epitaxial layers each include a flat first portion and a slopedsidewall portion. The sloped sidewall region is shown to be etched orgrown to a width that creates a pinch-off region as disclosed herein.Notably, the contact placement of the n-contact 1031 and p-contact 1026and the material grow to form the epitaxial layers minimizes carriertransport to the sloped sidewall and/or edges of the active layer 1016.

FIGS. 11A and B illustrate TFFC versions of LEDs 1100 with an attachedlens. LEDS 1100 may be formed from method 600. LED 1100 depicts an LEDfurther in the process from that of FIG. 10A with the epi structureflipped over and the substrate removed as described above. LED 1100includes a p-contact 1125 positioned adjacent to a p-layer 1120. P-layer1120 is located adjacent to EBL 1135, which is adjacent to active layer1115. N-layer 1110 is positioned adjacent to active layer 1115 distal toEBL 1135. N-contact 1130 is coupled to n-layer 1110. In between theepitaxial layers and n-contact 1130 is a dielectric insulator 1140.Dielectric insulator 1140 between n-layer 1110 and p-layer 1120 does notneed to passivate active layer 1115. Dielectric insulator 1140 mayoperate as an insulator and therefore may be cheaper and simpler toimplement. Adjacent to the n-layer 1110 is a micro-molded lens 1150.FIG. 11A depicts LED 1100 with the n-contact 1130 and dielectricinsulator 1140 extending approximately even with the p-contact 1125.FIG. 11B has the dielectric insulator 1140 removed while n-contact 1130extends slightly beyond n-layer 1110.

FIGS. 12A and B illustrate chip scale package (CSP) versions of LEDs1200 with the attached lens. LEDS 1200 may be formed from method 600.LED 1200 depicts a LED further in the process from that of FIG. 10A withthe epi structure flipped over. LED 1200 includes a p-contact 1225positioned adjacent to a p-layer 1220. P-layer 1220 is located adjacentto EBL 1235, which is adjacent to active layer 1215. N-layer 1210 ispositioned adjacent to active layer 1215 distal to EBL 1235. N-contact1230 is coupled to n-layer 1210. In between the epitaxial layers andn-contact 1230 is a dielectric insulator 1240. Dielectric insulator 1240between n-layer 1210 and p-layer 1220 does not need to passivate activelayer 1215. Dielectric insulator 1240 may operate as an insulator andtherefore may be cheaper and simpler to implement. Adjacent to then-layer 1210 is a transparent substrate 1245 with a micro molded lens1250 adjacent to transparent substrate 1245 distal to n-layer 1210.Transparent substrate 1245 may be thinned as would be understood tothose possessing an ordinary skill in the art. FIG. 12A depicts LED 1200with the n-contact 1230 and dielectric insulator 1240 extendingapproximately even with the p-contact 1225. FIG. 12B has the dielectricinsulator 1240 removed while n-contact 1230 extends slightly beyondn-layer 1210.

FIG. 13 illustrates an alternative LED 1300 embodiment requiring lessprocessing (p-side sidewall). Similar to LED 1000 of FIG. 10A, LED 1300includes a layered device including layers of a substrate 1305, n-layer1310, active layer 1315, EBL 1335, p-layer 1320, and p-contact 1325.N-contact 1330 may be provided over the n-layer 1310 and may extend ashigh or low on the device structure as needed to provide the necessaryelectrical connections and/or optical isolation between adjacent LEDs1300 in an array of LEDs. LED 1300 may be formed via method 600. LED1300 is depicted before removal of the substrate 1305 in method 600. LED1300 differs from LED 1000 in that in the process of making LED 1300there is a single etch performed that starts at a second flat region ofp-layer 1320. According to an alternative embodiment, no additional etchmay be performed as the p-side of p-layer 1320 at the sloped sidewallmay be thin to adequately reduce hole transport to active layer 1315.

FIG. 14A and FIG. 14B illustrate alternative embodiments for thetemplate pattern of the substrate (shown) or template pattern anglegenerally. FIG. 14A and FIG. 14B depict the LED 1000 of FIG. 10A. LED1000 includes a layered device including layers of a substrate 1405,n-layer 1010, active layer 1015, EBL 1035, p-layer 1020, and p-contact1025. N-contact 1030 may be provided around the layered device and mayextend as high or low on the device structure as needed to provide thenecessary electrical connections. As illustrated in FIG. 14A, substrate1405 is formed as substrate 1405.1. Substrate 1405.1 includes verticalsides that may be beneficial in certain growth conditions. Asillustrated specifically in FIG. 14B, substrate 1405 is formed assubstrate 1405.2. Substrate 1405.2 includes an inverted side-cut thatmay be beneficial in certain growth conditions.

FIGS. 15A-C illustrate embodiments for different cross-sections ofsubstrate (shown) or template patterns generally. FIGS. 15A-C depict theLED 1000 of FIG. 10A. LED 1000 includes a layered device includinglayers of a substrate 1005, n-layer 1010, active layer 1015, EBL 1035,p-layer 1020, and p-contact 1025. EBL 1035 may provide electron blockingas would be understood in the art and/or may provide a set-back in thegeometry of the configuration. N-contact 1030 may be provided around thelayered device and may extend as high or low on the device structure asneeded to provide the necessary electrical connections. The LED of FIG.15A is illustrated as a rectangular pattern. The LED of FIG. 15B isillustrated as a polygonal pattern. The LED of FIG. 15C is illustratedas a triangular pattern. Other shaped patterns may also be created.

FIG. 16A illustrates an embodiment of LED 1600 with isolated activeregion, e.g., light emitting layers, via “pinch-off”. Reference hereinto pinch-off indicates a change in thickness of a layer of the samematerial as positioned on a flat region versus a sloped region orsidewall. Similar to LED 1000 of FIG. 10A, LED 1600 includes a layereddevice including layers of a substrate 1605, n-layer 1610, active layer1615, EBL 1635, p-layer 1620, and p-contact 1625. N-contact 1630 may beprovided around the layered device and may extend as high or low on thedevice structure as needed to provide the necessary electricalconnections. LED 1600 may be formed via method 600. LED 1600 is depictedbefore removal of the substrate 1605 in method 600. LED 1600 includes arealization of pinch-off that implies epitaxial growth optimization,which is highlighted by a pinch-off zone on sloped sidewalls 1695.Notably, as shown in FIG. 16A, the sloped sidewalls of the n-layer 1610,active layer 1615, EBL 1635, p-layer 1620 may be etched or grown suchthat epitaxial layers of the sloped sidewall may have a thickness thatis less than 80% of their corresponding thickness in the first flatregion and/or second flat region. An exemplary pinch-off zone on thesloped sidewall 1695 has a structure in accordance with FIG. 16B in thatthere is a step-change in thickness of a given-layer from the flatregion to the sloped sidewall. In FIG. 16B, excerpted substrate 1605 hasa flat region 1606 and a sloped sidewall 1607. The n-layer has a firstportion 1610 a on the flat region 1606 having a first thickness and asecond portion 1610 b on the sidewall 1607 having a second thickness.The active layer has a first portion 1615 a adjacent to the flat region1606 (directly on the first portion 1610 a of the n-layer) having afirst thickness and a second portion 1615 b adjacent to the sidewall1607 (directly on the second portion 1610 b of the n-layer) having asecond thickness. The EBL layer has a first portion 1635 a adjacent tothe flat region 1606 (directly on the first portion 1615 a of the activelayer) having a first thickness and a second portion 1635 b adjacent tothe sidewall 1607 (directly on the second portion 1615 b of the activelayer) having a second thickness. The p-layer has a first portion 1620 aadjacent to the flat region 1606 (directly on the first portion 1635 aof the EBL layer) having a first thickness and a second portion 1620 badjacent to the sidewall 1607 (directly on the second portion 1635 ofthe EBL layer) having a second thickness. For any of the layers,independently, the second thickness is less than the first thickness. Inone or more embodiments, the second thickness is less than 80%, or 70%,or 60%, or 50%, or 40%, or 30%, or 20%, or 10%, or 5% of the firstthickness. For a given doping level, the electrical resistance of thep-layer is inversely proportional to the layer thickness, thus thereduction of thickness of the p-layer in the sloped region increaseselectrical resistance and reduces parasitic hole leakage currentsbetween the first region and the second region or sloped sidewalls. Forexample, a 50% reduction in thickness may increase the resistance by200% and reduce parasitic hole currents by a factor of 2. Similarreduction of the thickness of the QW active region in the slopedsidewall will increase the energy bandgap of the crystal in that region.The higher energy bandgap will create an energy barrier and confinecarriers to the first region. For example, a 50% decrease in QWthickness would increase the energy bandgap by ˜75 meV and provideeffective confinement. A second effect of the thinner QW active regionis to increase the forward voltage of the p-n junction in the slopedsidewalls. Parasitic hole currents that flow from the first region tothe sloped sidewalls will be blocked from flowing through the p-njunction in the sloped sidewalls. The combined effect of thinner p-layerand QW active region in the sloped sidewalls may effectively causegreater than 90% of a forward bias hole injection to be confined to thetop flat region of the LED 1600.

FIG. 17 illustrates a LED 1700 on a multilevel patterned substrate.Similar to LED 1000 of FIG. 10A, LED 1700 includes a layered deviceincluding layers of a substrate 1705, n-layer 1710, active layer 1715,EBL 1735, p-layer 1720, and p-contact 1725. N-contact 1730 may beprovided around the layered device and may extend as high or low on thedevice structure as needed to provide the necessary electricalconnections. LED 1700 may be formed via method 600. LED 1700 is depictedbefore removal of the substrate 1705 in method 600. LED 1700 includes anactive layer 1715 that does not necessarily include pinch-off. The areaof 1796 shows EBL 1735 having a portion on the sidewall whose thicknessis not less than the thickness on the flat region. LED 1700 may berealized using self-align features.

FIG. 18 illustrates an isolated LED 1800 realized through a multilevelpatterned substrate. Similar to LED 1000 of FIG. 10A, LED 1800 includesa layered device including layers of a substrate 1805, n-layer 1810,active layer 1815, EBL 1835, p-layer 1820, and p-contact 1825. N-contact1830 may be provided around the layered device and may extend as high orlow on the device structure as needed to provide the necessaryelectrical connections. LED 1800 may be formed via method 600. LED 1800is depicted before removal of the substrate 1805 in method 600. LED 1800may be realized using a multi-step pattern of substrate 1805, whichcomprises a first flat region 1807, a second flat region 1808, a thirdflat region 1809, a sloped sidewall 1808.1 connecting the first flatregion 1807 and the second flat region 1808, and a bottom sidewall1809.1 connecting the second flat region 1808 and the third flat region1809. On the first flat region 1807 is a first flat portion 1811.1 ofthe n-layer 1810. On the sloped sidewall 1808.1 is a second slopedportion 1811.2 of the n-layer 1810. On the second flat region 1808 is athird flat portion 1811.4 of the n-layer 1810. On the bottom sidewall1809.1 is a fourth pinched portion 1811.4 of the n-layer 1810. Thismulti-step substrate is described above with respect to FIG. 2B. LED1800 as depicted has no processing beyond the inner LED. As a result, anadditional epitaxial layer 1895 including a substrate 1805, anothergrowth of n-layer 1810.1, another growth of active layer 1815.1, anothergrowth of EBL 1835.1, and another growth of p-layer 1820.1 is formed.This design allows the deposition of fully isolated LEDs and the layersbelow may be ignored and removed, simplifying the wafer fabrication.

FIGS. 19A and 19B illustrate a monolithic TFFC array 1900 of LEDs 2000using phosphor conversion and optical isolation that does not requirepick and place. As is illustrated in FIG. 19A, a view from the lens sideof array 1900 is provided. As is illustrated in FIG. 19B, a view fromthe distal to the lens side of array 1900 is provided. Array 1900 isillustrated as an array of LEDs that is 4×4 with the fourth row beingdepicted as cut in half so that the internal structure of each LED 2000may be viewed. The specifics of each LED are provided in and describedwith respect to FIG. 20. In FIGS. 19A and B, there is a column on eachend of red LEDs 1901 of LEDs 2000. In between the two red columns is acolumn of green LEDs 1902 of LED 2000 and a column of blue LEDs 1903 ofLED 2000. Such a configuration enables RGB as understood in the art. Asshown in FIGS. 19A and 19B, epitaxial layers of each LED may extend froma first flat region shown towards the bottom of LED, to slopedsidewalls, and onto the second flat region adjacent to the respectivephosphor layer of each of the respective LEDs. Alternatively, the slopedsidewalls may be grown or etched such that a subset of the epitaxiallayers do not extend to the second flat region adjacent to respectivephosphor layers.

FIG. 20 illustrates a LED 2000 unit cell of monolithic TFFC array usingphosphor conversion and optical isolation. LED 2000 may be formed frommethod 600. LED 2000 includes a p-contact 2025 positioned adjacent to ap-layer 2020. P-layer 2020 is located adjacent to EBL 2035, which isadjacent to active layer 2015. N-layer 2010 is positioned adjacent toactive layer 2015 distal to EBL 2035. N-contact 2030 is coupled ton-layer 2010. Phosphor layer 2014 is included adjacent to n-layer 2010.In between the epitaxial layers and n-contact 2030, and surrounding anyexposed regions of phosphor layer 2014 is a dielectric insulator2040/optical isolator 2055/stiffener 2060. Adjacent to the phosphorlayer 2014 is a micro molded lens 2050 distal to n-layer 2410.Dielectric insulator 2040/optical isolator 2055/stiffener 2060 may bethree separate layers or may be a single layer that performs thefunction of a dielectric insulator, an optical insulator and astiffener. As shown in FIG. 20, epitaxial layers may extend from a firstflat region shown towards the bottom of LED 2000, to sloped sidewalls,and onto the second flat region adjacent to phosphor layer 2014.Alternatively, the sloped sidewalls may be grown or etched such that asubset of the epitaxial layers do not extend to the second flat regionadjacent to phosphor layer 2014.

FIGS. 21A and B illustrate a monolithic VTF array 2100 of LEDs 2200 inFIG. 22 using phosphor conversion and optical isolation that does notrequire pick and place. As is illustrated in FIG. 21A, a view from thelens side of array 2100 is provided. As is illustrated in FIG. 21B, aview from the distal side of array 2100 is provided. Array 2100 isillustrated as an array of LEDs that is 5×4 with the fourth row beingdepicted as cut in half so that the internals of each LED 2000 may beviewed. In array 2100 each column is offset from its neighbor so as tomisalign the LEDs 2200 in adjacent columns from each other. For example,columns 2101, 2103 and 2105 are aligned, while columns 2102 and 2104 areoffset approximately on half width of the LED 2200 (accounting for thespacing between LEDs 2200). The specifics of each LED are provided inand described with respect to FIG. 22. In FIGS. 21A and B, the oddcolumns 2101, 2103 and 2105 alternate between green LEDs 2200 and redLEDs 2200. The even columns 2102 and 2104 alternate between green LEDs2200 and blue LEDs 2200. Such a configuration enables RGB as understoodin the art. As shown in FIGS. 21A and 21B, epitaxial layers of each LEDmay extend from a first flat region shown towards the bottom of LED, tosloped sidewalls, and onto the second flat region adjacent to therespective phosphor layer of each of the respective LEDs. Alternatively,the sloped sidewalls may be grown or etched such that a subset of theepitaxial layers do not extend to the second flat region adjacent torespective phosphor layers.

FIG. 22 illustrates a LED 2200 unit cell of monolithic VTF array usingphosphor conversion and optical isolation. Similar conceptually to LED2000 of FIG. 20, LED 2200 may be formed from method 800. LED 2200includes a p-contact 2225 positioned adjacent to a p-layer 2220. P-layer2220 is located adjacent to EBL 2235, which is adjacent to active layer2215. N-layer 2210 is positioned adjacent to active layer 2215 distal toEBL 2235. N-contact 2230 is coupled to n-layer 2210 while beingpositioned separated from the other layers as described above withrespect to FIGS. 7 and 8. N-contact 2230 is configured to provideoptical isolation, analogous to 2055 of FIG. 20. Phosphor layer 2214 isincluded adjacent to n-layer 2210. The epitaxial layers are surroundedby a dielectric insulator 2240/stiffener 2260. Adjacent to then-phosphor layer 2214 is a micro molded lens 2250 distal to n-layer2210. Dielectric insulator 2240/stiffener 2260 may be separate layers ormay be a single layer that performs the function of a dielectricinsulator and a stiffener. As shown in FIG. 22, epitaxial layers mayextend from a first flat region shown towards the bottom of LED 2200, tosloped sidewalls, and onto the second flat region adjacent to phosphorlayer 2014. Alternatively, the sloped sidewalls may be grown or etchedsuch that a subset of the epitaxial layers do not extend to the secondflat region adjacent to phosphor layer 2014.

According to embodiments, a method for manufacturing an LED includesproviding a patterned substrate, the patterned substrate having a firstflat region and a second flat region on a recessed plane relative to thefirst flat region, and sloped sidewalls connecting the first flat regionand the second flat region. A first layer, of a plurality of layers of asemiconductor structure, may be grown over the first flat region at afirst growth rate. The first layer over the second flat region may begrown at a second growth rate. The first layer of over the slopedsidewalls may be grown at a third growth rate, the third growth ratebeing lower than the first growth rate and the second growth rate. Theangle of the sloped sidewalls and/or the crystallographic planeorientation may be modified to adjust the growth rate of a given regionor sidewall. For example, the crystallographic plane orientation of thesloped sidewalls may result in slower growth rate when compared to thecrystallographic plane orientation of the first flat region and/orsecond flat region. Growing the semiconductor structure may compriseproviding a UV emission wavelength over the patterned substrate. Greaterthan 90% of a forward bias hole injection may be confined to the firstflat region. The plurality of layers may comprise a p-type layer overthe sloped sidewalls, the p-type layer over the sloped sidewalls may athickness less than 80% of a thickness of the first flat region.

A resist may be applied to the to the semiconductor structure. Thepatterned substrate may be removed after growing the semiconductorstructure to create a first pocket and a phosphor layer may be depositedinto the first pocket. The width of the first flat region added to thesloped sidewalls may be between 1 micrometer and 10 micrometers and theheight of sloped sidewalls may between 1 micrometer and 10 micrometers.

According to embodiments, a method for manufacturing an LED includesgrowing an n-layer having a first flat region and a second flat regionon a recessed plane relative to the first flat region, and slopedsidewalls connecting the first flat region and the second flat region,growing at least one of an active layer and a p-layer over the firstflat region at a first growth rate, growing at least one of the activelayer and the p-layer over the second flat region at a second growthrate, and growing at least one of the active layer and the p-layer overthe sloped sidewalls at a third growth rate, the third growth rate beinglower than the first growth rate and the second growth rate.

An n-layer growth or regrowth may be grown over the first flat region atthe first growth rate, the second flat region at the second growth rate,and the sloped sidewalls at the third growth rate. Growing thesemiconductor structure may comprise providing a UV emission wavelengthover the n-layer. Greater than 90% of a forward bias hole injection mayconfined to the first flat region. The p-type layer over the slopedsidewalls may have a thickness that is less than 80% of the thickness ofthe first flat region. The width of the first flat region added to thesloped sidewalls may be between 1 micrometer and 10 micrometers. Theheight of sloped sidewalls may between 1 micrometer and 10 micrometers.

According to embodiments, a method for manufacturing a plurality of LEDsinclude providing a patterned substrate comprising a plurality ofpatterned areas (e.g., that are shaped as peaks) and non-patterned areas(e.g., that are shaped as valleys between peaks), growing a lightemitting structure comprising a plurality of layers, over the patternedsubstrate, at least one layer of the plurality of layers being thickerat both the first flat regions of the plurality of layers and the secondflat regions of the plurality of layers, compared to sloped sidewallsthat connects the first flat regions to the second flat regions,depositing a first resist to the light emitting structure to provideaccess to the substrate via first portions of the light emittingstructure without the resist, etching through the first portions of thelight emitting structure to the patterned substrate, and depositing ann-contact metal through the etched first portions of the light emittingstructure, the n-contact metal shaped to optically isolate LED emissionsfrom an adjacent LED.

The method may further include depositing a second resist to thesemiconductor structure, the second resist deposited onto to secondportions of the semiconductor structure such that a p-layer is exposedbetween sections of the second resist, and depositing p-contact metalsto produce p-contacts electrically coupled to the p-layer.

The method may further include bonding a thin film transistor (TFT)backplane to at least the n-contact metal and the p-contact metals,injecting an underfill to fill areas surrounding the p-contacts, then-contact, and the p-layer, and removing the growth substrate byinverting the manufactured structure to expose the n-layer. The width ofthe first flat region of the first LED added to the sloped sidewalls ofthe first LED may be between 2 micrometers and 10 micrometers.

The present embodiments and concepts with suitable modifications may beapplied to a range of light emitting material including both (Al)InGaN(Aluminum, Indium, Gallium, Nitride) and AlInGaP (Aluminum, Indium,Gallium, Phosphide) LEDs.

The singulated die embodiments may be used for all types of LEDsapplications, including a wide range of display sizes and moderate tolow pixel density, including, for example, large area monitors andbillboards and cellphones. The compact monolithic design is suitable forsmall high density, high performance arrays such as watches, projectorsand Virtual/Mixed/Augmented Reality devices. Optics may be added tocontrol emission pattern with >3 colors generated for custom displays.Flexible, curved displays are compatible with the teachings herein.White emitting phosphor mixtures may be used for illuminationapplications addressing various pixel combinations to tune colortemperature and radiation pattern through system optics. The intensityof some or all pixels may be varied in time to trigger external eventsor transmit information. Some pixels may be used as detectors while someare used as emitters. Optical patterns may be synchronized to externalsound frequencies for entertainment or to convert sound to an equivalentlight pattern. A touchscreen may be included in the display constructionand pressure signals may be coupled to light patterns. Two color rearautomotive lighting may be provided, e.g., the color may become a deeperred and brighter as brakes are more heavily applied. Generally, a colorshift may be used to transmit information such as external weatherconditions, temperature, etc. Automotive forward lighting units withcontrollable source patterns may be formed. Finally, the devices createdare scalable, limited only by the size and shape of the growthsubstrate.

FIG. 23 is a diagram of an example system 2300 that may be used toimplement all, some or portions of the embodiments described herein.System 2300 may correspond to any applicable display including, but notlimited to, a mobile device display, a computer display, an electronicdisplay, a television, virtual reality (VR) device, augmented reality(AR) device, a projector, a watch, or the like. It will be understoodthat the number of LEDs in an LED array in a device may vary dependingon the device such as, for example, in a television verses a watch. Inthe example illustrated in FIG. 23, the system 2300 may include aprocessor 2340, a memory 2350, storage 2320, one or more input devices2330, one or more output devices 2370, as well as one or more othercomponents. It will be understood that although the example system 2300of FIG. 23 discloses a plurality of components, one or more of thedisclosed plurality of components may be necessary to implement theembodiments disclosed herein. Additionally, a lighting system or displaymay include additional components than those that are shown in system2200.

The processor 2340 may include a central processing unit (CPU), agraphics processing unit (GPU), a CPU and GPU, and/or one or moreprocessor cores. The memory 2350 may include a volatile or non-volatilememory, for example, random access memory (RAM), dynamic RAM, or acache. The storage 2320 may include a fixed or removable storage, forexample, a hard disk drive, a solid state drive, an optical disk, or aflash drive. The one or more input devices 2330 may include, forexample, a keyboard, a keypad, a touch screen, a touch pad, a detector,a microphone, an accelerometer, a gyroscope, a biometric scanner, and/ora network connection (e.g., a wireless local area network card fortransmission and/or reception of wireless IEEE 802 signals). The one ormore output devices 2370 may include, for example, a display, a speaker,one or more lights, an antenna, and/or a network connection.

The display 2390 may be connected to the processor 2340 and may be adisplay as disclosed in accordance with the embodiments disclosedherein. For example, the LEDs within display 2390 may be manufactured inaccordance with FIG. 5, FIG. 6, FIG. 7, and/or FIG. 8 as disclosedherein. Further, the display 2390 may include LEDs within display 2390that are configured the same as or similar to the LEDs disclosed inFIGS. 9-18, 20 and 22. Further, the display 2290 may include an array ofLEDs within the display 2390, as shown in FIGS. 19 and 21.

As an example of the system 2300 in operation, the system 2300 may be amobile phone and the display 2390 may be a mobile phone screen thatincludes an array of LEDs in accordance with the embodiments disclosedherein. An input device 2330, such as a touch input component mayreceive an input to display a first content. The input device 2330 maygenerate a signal based on the input and provide the signal to theprocessor 2324. The processor may obtain a pointer location for thecorresponding input from the memory 2350 and may provide the pointerlocation to storage 2320. Storage 2320 may retrieve the content andprovide it to the processor 2340. The processor 2340 may provide signalsto a backplane contained within the display 2390 such that the backplaneindividually addresses LEDs within the display 2290 to visually providethe content.

While the system 2300 is shown as a single unit, one of ordinary skillin the art will recognize that the system 2300 can have portions thatare split between different locations. For example, the entire system2300 could be located on the board with the LEDs and/or sensors and/orall or portions of the system may be located on the board while otherelements may be located off board. Additionally, only some elements ofthe system 2300 may be used in an implementation. For example, a storagedevice and/or memory may not be needed.

FIG. 24 illustrates a LED 2400 unit cell of monolithic TFFC arrayincluding a transparent substrate. LED 2400 may be formed from method600. LED 2400 depicts a LED similar to that of FIG. 12A having asubstrate, preferably a transparent substrate 1245. LED 2400 includes ap-contact 2425 positioned adjacent to a p-layer 2420. P-layer 2420 islocated adjacent to EBL 2435, which is adjacent to active layer 2415.N-layer 2410 is positioned adjacent to active layer 2415 distal to EBL2435. N-contact 2430 is coupled to n-layer 2410. In between theepitaxial layers and n-contact 2430 is a dielectric insulator2440/optical isolator 2455/stiffener 2460. Adjacent to the transparentsubstrate 2445 is a micro molded lens 2450 distal to n-layer 2410.Dielectric insulator 2040/optical isolator 2055/stiffener 2060 may bethree separate layers or may be a single layer that performs thefunction of a dielectric insulator, an optical insulator and astiffener. As shown in FIG. 24, epitaxial layers may extend from a firstflat region of the substrate, to a sloped region, and onto a second flatregion of the substrate.

FIGS. 25A and 25B illustrate a monolithic TFFC array 2500 of LEDs 2400that does not require pick and place. As is illustrated in FIG. 25A, aview from the lens side of array 2500 is provided. As is illustrated inFIG. 25B, a view from the distal to the lens side of array 2500 isprovided. Array 2500 is illustrated as an array of LEDs that is 4×4 withthe fourth row being depicted as cut in half so that the internalstructure of each LED 2400 may be viewed. The specifics of each LED areprovided in and described with respect to FIG. 24. In FIGS. 25A and 25B,the LEDs 2400 are all the same color.

The methods provided may be implemented in a general purpose computer, aprocessor, or a processor core. Suitable processors include, by way ofexample, a general purpose processor, a special purpose processor, aconventional processor, a digital signal processor (DSP), a plurality ofmicroprocessors, one or more microprocessors in association with a DSPcore, a controller, a microcontroller, Application Specific IntegratedCircuits (ASICs), Field Programmable Gate Arrays (FPGAs) circuits, anyother type of integrated circuit (IC), and/or a state machine. Suchprocessors may be manufactured by configuring a manufacturing processusing the results of processed hardware description language (HDL)instructions and other intermediary data including netlists (suchinstructions capable of being stored on a computer readable media). Theresults of such processing may be mask works that are then used in asemiconductor manufacturing process to manufacture a processor whichimplements features of the disclosure.

The methods or flow charts provided herein may be implemented in acomputer program, software, or firmware incorporated in a non-transitorycomputer-readable storage medium for execution by a general purposecomputer or a processor. Examples of non-transitory computer-readablestorage mediums include a read only memory (ROM), a random access memory(RAM), a register, cache memory, semiconductor memory devices, magneticmedia such as internal hard disks and removable disks, magneto-opticalmedia, and optical media such as CD-ROM disks, and digital versatiledisks (DVDs).

What is claimed is:
 1. A light emitting diode (LED) device comprising: apocket defined by surfaces of a continuous epitaxial layer comprising:an n-layer, a p-layer, and an active layer between the n-layer and thep-layer; a p-contact in contact with the p-layer; and an n-contact incontact with the n-layer and isolated from the p-contact.
 2. The LEDdevice of claim 1, wherein the surfaces of the pocket comprise at leasttwo different crystallographic plane orientations.
 3. The LED device ofclaim 1, wherein the pocket is exposed upon removal of a growthsubstrate.
 4. The LED device of claim 1, wherein surfaces of the pocketcomprise submicron patterning.
 5. The LED device of claim 1, wherein thecontinuous epitaxial layer has at least a primary flat region, a slopedregion, and the sloped region comprises a pinch-off zone.
 6. The LEDdevice of claim 5, wherein a thickness of the n-layer in the slopedregion is less than 80% of a thickness of the n-layer in the primaryflat region.
 7. The LED device of claim 5, wherein a thickness of theactive layer in the sloped region is less than 80% of a thickness of theactive layer in the primary flat region.
 8. The LED device of claim 5,wherein a thickness of the p-layer in the sloped region is less than 80%of a thickness of the p-layer on the primary flat region.
 9. The LEDdevice of claim 1 further comprising a light-converting phosphormaterial in the pocket.
 10. The LED device of claim 1 further comprisinga high-refractive index material in the pocket.
 11. The LED device ofclaim 1, wherein the continuous epitaxial layer further comprises asecondary flat region such that the sloped region extends from theprimary flat region to the secondary flat region.
 12. A light emittingdiode (LED) device comprising: a pocket defined by surfaces of acontinuous epitaxial layer comprising: an n-layer, a p-layer, and anactive layer between the n-layer and the p-layer, the surfaces of thepocket comprising at least three different crystallographic planeorientations; a light-converting phosphor material or a high-refractiveindex material in the pocket; a p-contact in contact with the p-layer;and an n-contact in contact with the n-layer and isolated from thep-contact.
 13. The LED device of claim 12, wherein the continuousepitaxial layer has a primary flat region, a sloped region thatcomprises a pinch-off zone, and a secondary flat region such that thesloped region extends from the primary flat region to the secondary flatregion.
 14. The LED device of claim 13, wherein a thickness of then-layer in the sloped region is less than 80% of a thickness of then-layer in the primary flat region and/or a thickness of the activelayer in the sloped region is less than 80% of a thickness of the activelayer in the primary flat region and/or a thickness of the p-layer inthe sloped region is less than 80% of a thickness of the p-layer on theprimary flat region.
 15. An array of light emitting diodes (LEDs)comprising: a plurality of LED devices according to claim 1 attached toa backplane.
 16. The array claim 15, wherein the backplane is a thinfilm transistor (TFT) backplane.
 17. The array of claim 15, wherein thebackplane is configured to individually address each of the plurality ofLED devices.
 18. The array of claim 15, wherein at least one of thefollowing is adjustable: a color temperature, an intensity, or a sourcepattern.
 19. The array of claim 15 effective as a thin film flip chip(TFFC) array.
 20. The array of claim 15 effective as a verticalinjection thin film (VTF) array.